Patent
Processor with reconfigurable arithmetic data path
George Landers,Earle W. Jennings,Tim B. Smith,Glen Haas +3 more
- 20 Jan 1998
159
TL;DR: In this paper, a reconfigurable processor includes at least three (3) MacroSenquencers (10-16) which are configured in an array, each of which is operable to receive on a separate one of four buses (18) an input from other three MacroSequencers and from itself in a feedback manner.
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Abstract: A reconfigurable processor includes at least three (3) MacroSenquencers (10-16) which are configured in an array. Each of the MacroSequencers is operable to receive on a separate one of four buses (18) an input from the other three MacroSequencers and from itself in a feedback manner. In addition, a control bus (20) is operable to provide control signals to all of the MacroSequencers for the purpose of controlling the instruction sequence associated therewith and also for inputting instructions thereto. Each of the MacroSequencers includes a plurality of executable units having inputs and outputs and each for providing an associated execution algorithm. The outputs of the execution units are input to an output selector which selects the outputs for outputs on at least one external output and on at least one feedback path. An input selector (66) is provided having an input for receiving at least one external output and at least the feedback path. These are selected between for input to select ones of the execution units. An instruction memory (48) contains an instruction word that is operable to control configurations of the datapath through the execution units for a given instruction cycle. This instruction word can be retrieved from the instruction memory (48), the stored instructions therein sequenced through to change the configuration of the datapath for subsequent instruction cycles.
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Citations
Securing software by enforcing data-flow integrity
Miguel Castro,Manuel Costa,Tim Harris +2 more
- 06 Nov 2006
TL;DR: An efficient implementation of data-flow integrity enforcement that uses static analysis to reduce instrumentation overhead is described and can be applied automatically to C and C++ programs without modifications, it does not have false positives, and it has low overhead.
Patent
Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
Paul L. Master,Eugene Hogenauer,Walter James Scheuermann +2 more
- 11 Mar 2002
TL;DR: In this article, a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing is proposed, which includes a plurality of heterogeneous computational elements coupled to an interconnection network.
256
Patent
Devices and methods with programmable logic and digital signal processing regions
Martin Langhammer,Greg Starr,Chiao Kai Hwang +2 more
- 28 Jan 2003
TL;DR: A programmable logic integrated circuit device (PLD) includes a dedicated (i.e., at least part hard-wired) digital signal processing region for performing or at least helping to perform digital signal-processing tasks that are unduly inefficient to implement in the more general-purpose PLC and/or that, if implemented in the PLC, would operate too slowly as discussed by the authors.
204
Patent
Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements
Paul Master,Stephen Smith,John Watson +2 more
- 30 Sep 2005
TL;DR: In this article, the configuration of a new category of integrated circuitry for adaptive computing is discussed and various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information.
161
Patent
Task definition for specifying resource requirements
Ramana V. Katragadda,Paul L. Spoltore,Ric Howard +2 more
- 29 Aug 2002
TL;DR: Task definitions are used by a task scheduler and prioritizer to allocate task operations to a plurality of processing units as mentioned in this paper, where the task definition is an electronic record that specifies resources needed by, and other characteristics of, a task to be executed.
121
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