Patent
Processor having compression and encryption circuitry
Robert J. Grabon
- 11 Sep 1996
143
TL;DR: A data processing system (100) includes a data processor or CPU (102) having decompression circuitry (208, 212, 212) and decryption circuitry (210, 214, 214) that operates on compressed/encrypted data to produce decompressed and decrypted data as mentioned in this paper.
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Abstract: A data processing system (100) includes a data processor or CPU (102) having decompression circuitry (208, 212) and decryption circuitry (210, 214) that operates on compressed/encrypted data to produce decompressed and decrypted data. The data processing system includes memory (104) in which instructions and data are stored in a compressed (110) and/or encrypted (114) format. The CPU (102) retrieves the compressed/encrypted data over a system bus (106). A bus interface unit (200) within the CPU (102) receives the compressed/encrypted data, decompresses and decrypts the data and stores the data in cache memory (202). An execution unit (204) and other components within the CPU (102) retrieve the decompressed and decrypted data and operate upon it. Alternatively, upon retrieval of compressed/encrypted data from memory (104) the data is stored in cache memory (202) in its compressed/encrypted format. Upon retrieval by the execution unit (204), the data is decompressed and decrypted in preparation for execution by the execution unit (204). A data processing system (400) of the present invention requires that the CPU (402) decrypt encrypted data. Thus, any devices accessing data in the system (400) over a network (426) without decryption by the CPU (402) retrieve encrypted data that cannot otherwise be decrypted.
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Citations
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