Patent
Processor, controller, and method for locking code in cache
William V. Miller
- 01 Feb 2008
3
TL;DR: In this article, a processor comprises a cache and a cache controller, where the cache is configured to store a temporary copy of code residing in main memory, where each cache way is further divided into a number of cache way portions.
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Abstract: Systems and methods are disclosed for locking code in cache. In one embodiment, a processor comprises a cache and a cache controller. The cache is configured to store a temporary copy of code residing in main memory. Also, the cache is divided into a number of cache ways, where each cache way is further divided into a number of cache way portions. The cache controller is configured to utilize a first signal and a second signal. The first signal designates one of the cache ways as a partial cache way and the second signal defines which ones of the cache way portions of the partial cache way are to be locked.
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Citations
Patent
Cache line allocation method and system
Bingxu Gao,Xian Chen +1 more
- 16 Apr 2012
TL;DR: In this article, a cache line allocation method was proposed, wherein the cache is coupled to a graphic processing unit and the cache comprising a plurality of cache lines, each cache line stores one of a pluralityof instructions, and the method comprising the steps of: putting the plurality of instructions in whole cache lines; locking the entire cache lines if an instruction size is less than a cache size; locking a first number of caches lines when the instruction size was larger than the cache size and a difference between the instruction and cache size was less than or equal to a threshold.
2
Patent
Cache access method and system
Bingxu Gao,Xian Chen +1 more
- 01 Nov 2012
TL;DR: In this paper, a cache access method is proposed to determine whether each of a plurality of data hits a cache according to a read request for the plurality of the data; and at least one entry of the cache is left unlocked while other entries are locked when some of the missing data miss the cache and the length of the missed data is greater than the cache length.