Patent
Processor-cache protocol using simple commands to implement a range of cache configurations
Dan W. Patterson,Bindi Prasad,Gurbir Singh,Peter D. MacWilliams,Steve Hunt,Phil G. Lee +5 more
- 06 May 1997
39
TL;DR: In this article, a processor-cache protocol supporting multiple cache configurations is described, where the processor including its cache control circuit is coupled to a cache bus. And a second level cache memory is also coupled to the cache bus by issuing commands that are executed by the second-level cache.
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Abstract: A computer system having a processor-cache protocol supporting multiple cache configurations is described. The computer system has a processor having a cache control circuit to control multiple cache memory circuits. The processor including its cache control circuit is coupled to a cache bus. A second level cache memory is also coupled to the cache bus. The cache control circuit controls the second level cache by issuing commands that are executed by the second level cache.
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