Patent
Processor apparatus and conditional branch processing method
Masaru Terashima
- 07 Jan 2009
12
TL;DR: In this article, a branch condition storage unit with a plurality of storage regions in each of which the branch condition set by a condition setting instruction is stored is described, including an instruction decoder that decodes an instruction code, an instruction memory that stores therein the instruction code and an operation register used by a processor for operation, a branch comparison unit that performs a comparison operation for each of branch conditions, a conditional branch determination unit that makes a determination whether or not to perform program branching in a condition branch instruction, a selector that makes selection between a branch destination address and a next
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Abstract: Disclosed is a processor apparatus including a branch condition storage unit having a plurality of storage regions in each of which a branch condition set by a condition setting instruction is stored, an instruction decoder that decodes an instruction code, an instruction memory that stores therein the instruction code, an operation register used by a processor for operation, a branch condition comparison unit that performs a comparison operation for each of branch conditions, a conditional branch determination unit that makes a determination whether or not to perform program branching in a conditional branch instruction, a selector that makes selection between a branch destination address and a next instruction address, based on an output value of the condition branch determination unit, and a program counter that indicates a processor instruction executing position. The branch condition specified by the condition setting instruction is stored in one of the storage regions in the branch condition storage unit 1 specified by the condition setting instruction. When the conditional branch instruction is executed, individual determinations on a plurality of the branch conditions stored in the branch condition storage unit are made. Among the branch conditions that simultaneously hold, the branch address corresponding to the branch condition stored in a predetermined one of the storage regions in the branch condition storage unit is selected from the branch address storage unit, and branching to the branch address is performed.
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Citations
Patent
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TL;DR: In this article, an apparatus and method for calculating flag bits is described, which can be used to evaluate whether a branch is to be taken or not in a processor utilizing branch predication, and the apparatus can be coupled with a condition code associated with an instruction, and flag bits generated responsive to execution of the instruction.
5
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Patent
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Patent
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34
Patent
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Fukuda Hideaki
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