Patent
Processing unit for multiplying two mathematical quantities including at least one complex multiplier
Thomas M. King,Sam M. Daniel +1 more
- 24 Mar 1980
29
TL;DR: In this paper, a processing unit includes at least one complex multiplier having hour multiplying circuits for multiplying the real and imaginary components of two complex vectors and combining the products to produce a complex output vector.
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Abstract: The processing unit includes at least one complex multiplier having hour multiplying circuits for multiplying the real and imaginary components of two complex vectors and combining the products to produce a complex output vector. Representing the input complex vectors by (A+jB) and (C+jD) the output complex vector becomes (AC-BD)+j(BC+AD). The combining circuits can be switched so that one of the input complex vectors is conjugated and the output complex vector becomes (AC+BD)+j(BC-AD). Thus, the present processing unit can provide the dot product of two complex vectors or the like.
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Citations
Patent
Method and system in a data processing system for loading and storing vectors in a plurality of modes
Ramesh C. Agarwal,Randall Dean Groves,Fred G. Gustavson,Mark Johnson,Terry L. Lyon,Brett Olsson,James B. Shearer +6 more
- 04 Jan 1995
TL;DR: In this paper, a vector having a plurality of elements is stored in an input storage area, wherein the vector elements are stored in a first pattern, and the elements are transferred, in first order, from the input storage areas into a vector register interface unit.
155
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Digital signal processor architecture optimized for performing fast fourier transforms
Mohit K. Prasad,Hosahalli R. Srinivas +1 more
- 30 Jun 1997
TL;DR: In this article, a digital signal processor architecture for fast Fourier transform (FFT) algorithms is presented. But the architecture is not suitable for high-dimensional (HDF) data.
90
Patent
Pipelined linear array of processor elements for performing matrix computations
Alan Joel Greenberger
- 21 Apr 2000
TL;DR: A pipelined linear array of processor elements (PEs) for matrix computations in an efficient manner is presented in this article, where each PE includes arithmetic circuitry for performing multiply, combine and accumulate operations and a register file for storing inputs and outputs of the arithmetic circuitry.
69
Patent
Cordic complex multiplier
Matthew O'Donnell,Ernest Engeler William +1 more
- 31 May 1988
TL;DR: In this paper, a CORDIC subsystem for multiplication of two complex digital numbers B and C, where one number is the sum of real and imaginary data portions, expressed in rectangular form (say Cr or CI), and the other number can be expressed in the rectangular form or can be represented by magnitude data expressed in polar form, is presented.
64
Patent
Multiplier-accumulator circuit using latched sums and carries
Mordecai Barkan
- 13 Nov 1984
TL;DR: In this paper, a pipelining-based vector dot multiplier is proposed for positive integer dot multiplication, where a latch interconnects the carryout of each adder in a row to the carry-in of another adders in the same row, and the sum output is accumulated in an adder according to the length of the vectors to be processed.
58
References
Patent
Fast fourier transform stage using floating point numbers
Lloyd William Martinson,Richard James Smith +1 more
- 27 Jun 1974
TL;DR: In this paper, a complex Fourier operation of multiplying a fixed complex number by a floating point complex number and adding to the resulting product another floating-point complex number is described.
45
Patent
Complex filters, convolvers, and multipliers
Bond James W,Speiser Jeffrey M +1 more
- 27 Sep 1974
TL;DR: In this paper, a complex multiplier consisting of four signal summers, two means for inverting a signal, and three signal multipliers is defined, and the output signal of the fourth summer is equal to the magnitude of the real part of the same multiplied complex signals.
26
Patent
Specialized microprocessor for computing the sum of products of two complex operands
Epenoy Gabriel Irenee,Kuhne Roland,Laurent Bernard,Philippe Thirion +3 more
- 29 Nov 1978
TL;DR: In this article, a specialized processor capable of computing a sum of products S = Σ±Pi where every product Pi is the product of two n-bit complex operands Ai+j Bi, the multiplier, and Ci+j Di, the multiplicand, where j=√-1.
20
Patent
Method and apparatus for the digital detection of predetermined frequencies
Ellert Schaepman
- 19 Apr 1972
TL;DR: In this article, a process and apparatus are provided whereby a signal containing mixed frequencies is sampled in equal time intervals T which are smaller than the half cycle of the highest frequency contained in the mixture of frequencies, obtaining a value from each sampling operation, wherein this value, considered as a real magnitude is added to a complex value calculated from preceding sampling operations; the resulting complex value is multiplied by a constant complex value ej T, in which Omega is the predetermined frequency.
19
Patent
Five-stage four-bit complex multiplier
James R. Gaskill,Lawrence R. Weill +1 more
- 18 Aug 1976
TL;DR: In this paper, a multipliers for complex numbers using four 3-stage 4 × 4 bit 2's complement multipliers and a modified adder and subtractor is presented. But the multipliers are not used in this paper.
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