Patent
Process for making polycide structures
Stanley Roberts,Francis Roger White +1 more
- 16 May 1984
43
TL;DR: An improved method for making polycide structures for use in electrode and wiring interconnection applications is described in this paper, which consists of depositing a layer of polysilicon on an insulating layer and forming on this poly-silicon layer a silicide structure and a silicon capping layer.
read more
Abstract: An improved method for making polycide structures for use in electrode and wiring interconnection applications. It includes depositing a layer of polysilicon on an insulating layer and forming on this polysilicon layer a silicide structure and a silicon capping layer. The deposited layers are defined and etched through dry etching techniques using a dry etching mask made of a refractory metal that does not form a volatile halide in a dry etching environment. Metals with such characteristics include cobalt (Co), nickel (Ni), iron (Fe), and manganese (Mn). The metal mask and the other deposited layers may be formed and defined using a photoresist mask as a deposition mask formed to be compatible with lift-off techniques. The silicide may be deposited either through a chemical vapor deposition process or through evaporation techniques. If it is formed through the co-evaporation of metal and silicon, then the structure is subjected to a low temperature reaction annealing step at a temperature between 500° and 600° C. prior to dry etching. To avoid a diffusion of the metal mask into the silicon layer, during this low temperature annealing, the process provides for the formation of a diffusion barrier layer between the metal mask and the silicon layer. Following the removal of the metal mask and the diffusion barrier layer, the structure is annealed at a temperature sufficient to cause the homogenization of the silicide layer.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
Patent
Method for forming metal layer using atomic layer deposition
Sang-Bom Kang,Yun-Sook Chae,Chang-Soo Park,Sang-In Lee +3 more
- 15 Dec 1998
TL;DR: In this paper, a method for forming a metal layer using an atomic layer deposition process was proposed, in which a sacrificial metal atomic layer is formed on a semiconductor substrate by reacting a precursor containing a metal with a reducing gas, and a metal atom is formed of metal atoms separated from a metal halide gas.
454
Patent
Rapid thermal cvd apparatus
Daniel L. Brors,Larry R. Lane,Mark W. Goldsborough,Jason M. Samsel,Max Van Mastrigt,Robert Foster +5 more
- 15 Jan 1987
TL;DR: In this article, a chemical vapor deposition apparatus for coating semiconductor wafers, the wafer is held face down in the reaction chamber, and a radiant heat source is placed in a radial pattern to improve heating uniformity.
65
Patent
Chemical vapor deposition apparatus
Max Van Mastrigt
- 03 Dec 1985
TL;DR: A chemical vapor deposition apparatus includes a gas mixing chamber and a water-cooled reaction chamber with adjustable watercooled baffle between them as discussed by the authors, where a wafer is clamped face down to a chuck and inert gas such as helium is forced between the chuck and the wafer to insure proper heat conduction from chuck to wafer.
58
Patent
Salicide process for forming low sheet resistance doped silicon junctions
Kwangwoo Choi,Stanley Roberts +1 more
- 25 Oct 1985
TL;DR: In this article, a patterned silicide layer overlying a processed semiconductor substrate, the substrate having insulator regions and insulator-free regions on an exposed surface thereof, is formed.
30
Patent
Semiconductor element and manufacture thereof
Richard Norman Campbell,Michael Kevin Thompson,Elizabeth Ann Smith +2 more
- 22 Apr 1988
TL;DR: In this paper, a lift-off mask is formed on a first region of a layer of polysilicon and a first dopant is implanted into second regions of the poly-silicon which are adjacent the first region, and then the liftoff mask and the respective part of the layer of silicide which is deposited thereover are removed.
24
References
1 µm MOSFET VLSI technology: Part VII—Metal silicide interconnection technology—A future perspective
B.L. Crowder,S. Zirinsky +1 more
TL;DR: An alternative approach which combines a doped polycrystalline silicon layer with a high-conductivity metal silicide such as WSi2(polycide) is described, which is demonstrated to provide at least an order of magnitude improvement in interconnection resistance relative to polycrystaline silicon.
175
Patent
Method for providing a metal silicide layer on a substrate
Billy L. Crowder,Stanley Zirinsky +1 more
- 30 Jun 1977
TL;DR: In this article, a method for providing on a substrate a layer of a metal silicide such as molybdenum silicide and tantalum silicides and/or tungsten silicide, was presented, which includes coevaporating silicon and the respective metal onto a substrate, and then heat treating the substrate to form the metal.
106
Patent
Doped polysilicon silicide semiconductor integrated circuit interconnections
Billy L. Crowder,Arnold Reisman +1 more
- 01 Mar 1979
TL;DR: An improved interconnection for semiconductor integrated circuits is provided by a member made of doped polycrystalline silicon and metal silicide that provides the simultaneous advantages of high conductivity and reduced overlap capacitance in multilayer integrated circuit devices as discussed by the authors.
100
Patent
Fabrication method for integrated circuits with polysilicon lines having low sheet resistance
F.H. Gaensslen
- 11 Nov 1977
TL;DR: In this paper, a method and structure for polysilicon lines which include a silicide layer for providing a low sheet resistance was proposed, which may be employed in a polysilino gate MOSFET process for integrated circuits as well as other integrated structures.
87
Patent
Cobalt silicide metallization for semiconductor integrated circuits
Hyman Joseph Levinstein,Shyam P. Murarka,Ashok Kumar Sinha +2 more
- 27 Aug 1981
TL;DR: In this paper, a cobalt layer is sintered at about 400° C. to 500° C., on a patterned semiconductor wafer having exposed polycrystalline (14 or monocrystalline) silicon portions, as well as exposed oxide (15 or 25) portions.
78
Related Papers (5)
Fu-Tai Liou,Robert O. Miller,Mohammed M. Farohani,Han Yu-Pin +3 more
- 08 Jun 1989
Dennis J. Yost,Thomas D. Bonifield,Roc Blumenthal +2 more
- 13 Oct 1993
Stanley Wolf,Richard N. Tauber +1 more
- 01 Jan 1986