Proceedings Article10.1145/512529.512535
Preference-directed graph coloring
Akira Koseki,Hideaki Komatsu,Toshio Nakatani +2 more
- 17 May 2002
- Vol. 37, Iss: 5, pp 33-44
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TL;DR: A new framework of register allocation based on Chaitin-style coloring is described, focused on maximizing the chances for live ranges to be allocated to the most preferred registers while not destroying the colorability obtained by graph simplification.
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Abstract: This paper describes a new framework of register allocation based on Chaitin-style coloring Our focus is on maximizing the chances for live ranges to be allocated to the most preferred registers while not destroying the colorability obtained by graph simplification Our coloring algorithm uses a graph representation of preferences called a Register Preference Graph, which helps find a good register selection We then try to relax the register selection order created by the graph simplification The relaxed order is defined as a partial order, represented using a graph called a Coloring Precedence Graph Our algorithm utilizes such a partial order for the register selection instead of using the traditional simplification-driven order so that the chances of honoring the preferences are effectively increased Experimental results show that our coloring algorithm is powerful to simultaneously handle spill decisions, register coalescing, and preference resolutions
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Citations
A generalized algorithm for graph-coloring register allocation
Michael D. Smith,Norman F. Ramsey,Glenn Holloway +2 more
- 09 Jun 2004
TL;DR: This work presents a generalization of graph-coloring register allocation that handles two characteristics commonly found in commercial architectures, and adapts easily to a new target machine, requiring only the sets of names in the registers and a map of the register aliases.
A global progressive register allocator
David Ryan Koes,Seth Copen Goldstein +1 more
- 11 Jun 2006
TL;DR: An expressive model of global register allocation based on multicommodity network flows that explicitly represents spill code optimization, register preferences, copy insertion, and constant rematerialization, and a more elaborate progressive allocator that uses Lagrangian relaxation to compute the optimality of its allocations.
Nearly optimal register allocation with PBQP
Lang Hames,Bernhard Scholz +1 more
TL;DR: A new heuristic for PBQP is presented which significantly improves the quality of its register allocations and extends the range of viable target architectures and a new branch-and-bound technique is introduced that is able to find optimal register allocations.
40
Code Size Optimization for Embedded Processors
Neil Edward Johnson
- 01 Jan 2004
TL;DR: This thesis develops the Value State Dependence Graph as a powerful intermediate form and shows how procedural abstraction can be advantageously applied to the VSDG, and presents a method for using these instructions to reduce code size by provisionally combining loads and stores before code generation.
Evolution of a java just-in-time compiler for IA-32 platforms
Toshio Suganuma,Takeshi Ogasawara,Kiyokuni Kawachiya,Mikio Takeuchi,Kazuaki Ishizaki,Akira Koseki,Tatsushi Inagaki,Toshiaki Yasue,Motohiro Kawahito,Tamiya Onodera,Hideaki Komatsu,Toshio Nakatani +11 more
TL;DR: The design and implementation of the JIT compiler for IA-32 platforms by focusing on the recent advances achieved in the past several years is described, including the dynamic optimization framework, which focuses the expensive optimization efforts only on performance-critical methods, thus helping to manage the total compilation overhead.
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Efficiently computing static single assignment form and the control dependence graph
TL;DR: In this article, the authors present new algorithms that efficiently compute static single assignment forms and control dependence graphs for arbitrary control flow graphs using the concept of {\em dominance frontiers} and give analytical and experimental evidence that these data structures are usually linear in the size of the original program.
Register allocation & spilling via graph coloring
TL;DR: In a previous paper as mentioned in this paper, we reported the successful use of graph coloring techniques for doing global register allocation in an experimental PL/I optimizing compiler, when the compiler cannot color the...
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Improvements to graph coloring register allocation
TL;DR: This paper describes two improvements to Chaitin-style graph coloring register allocators, and provides a detailed description of optimistic coloring and rematerialization, and presents experimental data to show the performance of several versions of the register allocator on a suite of FORTRAN programs.
429
The priority-based coloring approach to register allocation
Fred C. Chow,John L. Hennessy +1 more
TL;DR: The detailed algorithms for a priority-based coloring approach are presented and are contrasted with the basic graph-coloring algorithm and various extensions to the basic algorithms are also presented.
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