Proceedings Article10.1109/MWSCAS.2007.4488749
Predicting processor performance with a machine learnt model
Azam Beg
- 01 Aug 2007
- pp 1098-1101
TL;DR: A machine learnt (neural network/NN) model is proposed for estimating the execution performance of a superscalar processor with over 85% accuracy when tested with six SPEC2000 CPU integer benchmarks.
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Abstract: Architectural simulators are traditionally used to study the design trade-offs for processor systems. The simulators are implemented in a high-level programming language or a hardware descriptive language, and are used to estimate the system performance prior to the hardware implementation. The simulations, however, may need to run for long periods of time for even a small set of design variations. In this paper, we propose a machine learnt (neural network/NN) model for estimating the execution performance of a superscalar processor. Multiple runs for the model are finished in less than a few milliseconds as compared to days or weeks required for simulation-based methods. The model is able to predict the execution throughput of a processor system with over 85% accuracy when tested with six SPEC2000 CPU integer benchmarks. The proposed model has possible applications in computer architecture research and teaching.
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Citations
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- 01 Jan 2008
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A neural model for processor-throughput using hardware parameters and software's dynamic behavior
Azam Beg,P. W. Chandana Prasad,Ashutosh Kumar Singh,Arosha Senanayake +3 more
- 01 Nov 2012
TL;DR: An NN model for processor performance (IPC) prediction that uses a larger set of input parameters (especially the software parameters) than the prior models and finds PCA to be a more useful technique than correlation and graphical analysis for dimension reduction.
2
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TL;DR: Machine learning addresses many of the same research questions as the fields of statistics, data mining, and psychology, but with differences of emphasis.
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Ashutosh S. Dhodapkar,James E. Smith +1 more
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TL;DR: Threedynamic program phase detection techniques are compared- using instruction working sets, basic block vectors (BBV), and conditional branch counts to show that techniques based on procedure granularities don't perform as well as those based on instruction or basic block granularity.
A Predictive Performance Model for Superscalar Processors
P. J. Joseph,Kapil Vaswani,Matthew J. Thazhuthaveetil +2 more
- 09 Dec 2006
TL;DR: The use of empirical non-linear modeling techniques to assist processor architects in making design decisions and resolving complex trade-offs and can potentially replace detailed simulation for common tasks such as the analysis of key microarchitectural trends or searches for optimal processor design points.
Theoretical modeling of superscalar processor performance
Derek B. Noonburg,John Paul Shen +1 more
- 30 Nov 1994
TL;DR: A theoretical model of superscalar processor performance is proposed that is compared to simulated performance for six benchmarks from the SPEC 92 suite on several configurations of the IBM RS/6000 instruction set architecture.
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