Journal Article10.1145/371254.371263
POSE: a parallel object-oriented synthesis environment
TL;DR: POSE can be applied especially to system-level synthesis, whose targets can be parallel computer architectures, systems-on-chip, or embedded systems, and can be easily integrated with other heuristic design methodologies to allow increased design efficiency.
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Abstract: Design automation tools and methodologies always encounter a problem of how systems may be designed efficiently, including issues such as static modeling and dynamic manipulation of system parts. With the rapid progress of design technology, the continuously increasing number of different choices per system part and the growing complexity of today's systems, the efficiency of the design environment is not only a major concern now, but will also be a demanding problem in the near future. In contrast to heuristic methods, a novel environment called POSE is proposed that increases efficiency during design without losing optimality in the final design results. System parts are modeled using the popular object-oriented modeling technique and are dynamically manipulated using the parallel design technique. A complete integration of object-oriented and parallel techniques is one of the major feature of POSE. Common problems related to parallel design such as emptiness and deadlock are also elegantly solved within POSE. Experimental results and formal analysis based on POSE all show its practical and theoretical usefulness. POSE can be used at any level of synthesis as long as off-the-shelf building-blocks manipulation is required. POSE can be applied especially to system-level synthesis, whose targets can be parallel computer architectures, systems-on-chip, or embedded systems. We will show how POSE has been applied to ICOS, a recently proposed synthesis methodology. Furthermore, POSE can be easily integrated with other heuristic design methodologies to allow increased design efficiency.
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Citations
Formal synthesis and code generation of embedded real-time software
Pao-Ann Hsiung
- 25 Apr 2001
TL;DR: In this work, a formal method based on Time Free-Choice Petri Nets (TFCPN) is proposed for ERTS synthesis, and an application example is given to illustrate the feasibility of the proposed TFCPN-based formal method.
Hardware-software timing coverification of concurrent embedded real-time systems
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- 01 Mar 2000
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