PixelFlow: high-speed rendering using image composition

TL;DR: A classification scheme is described that is based on where the sort from object coordinates to screen coordinates occurs, which it is believed is fundamental whenever both geometry processing and rasterization are performed in parallel.

TL;DR: HOM for visibility culling on complex models with high depth complexity uses an object space bounding volume hierarchy and a hierarchy of image space occlusion maps to cull away a portion of the model not visible from the current viewpoint.

TL;DR: The design, programming interface, and implementation of a very efficient user-programmable vertex engine embedded in the broader fixed function pipeline, supported by transparent multi-threading and bypassing to preserve parallelism and performance is described.

TL;DR: This paper reports on a variety of algorithms that exploit a tree of one-bit adders that can evaluate linear expressions Ax+By+C for every pixel simultaneously, as fast as the ALUs and the memory circuits can accept the results.

TL;DR: A system architecture for realtime display of shaded polygons that heavily leverages parallelism in several forms: pipeline, vector, and array processing, which is unique in providing efficient and balanced graphics that support interactive design and manipulation of solid models.

TL;DR: A CMOS output pad driver circuit is described that automatically series-terminates a driven line in the line's characteristic impedance, allowing the circuit to compensate for both chip and board level fabrication variations.

TL;DR: The architecture and initial algorithms for Pixel-Planes 5, a heterogeneous multi-computer designed both for high-speed polygon and sphere rendering (1M Phong-shaded triangles) are introduced.