Proceedings Article10.1145/166181.166188
Pixel merging for object-parallel rendering: a distributed snooping algorithm
Michael Cox,Pat Hanrahan +1 more
- 01 Nov 1993
- pp 49-56
31
TL;DR: An expected-case log (d/sup -/)A algorithm for pixel merging that uses network broadcast is presented and discussed, and the algorithm's applicability to shared-memory bus architectures is discussed.
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Abstract: In the purely object-parallel approach to multiprocessor rendering, each processor is assigned responsibility to render a subset of the graphics database. When rendering is complete, pixels from the processors must be merged and globally z-buffered. On an arbitrary multiprocessor interconnection network, the straightforward algorithm for pixel merging requires d/sup -/A total network bandwidth per frame, where d/sup -/ is the depth complexity of the scene and A is the area of the screen or window. This algorithm is used by the Kubota Pacific Denali and appears to be used by the Evans and Sutherland Freedom series. An alternative algorithm, the PixelFlow algorithm, requires nA network bandwidth per frame, where n is the number of processors. But the merging is pipelined in PixelFlow so that each network link must only support A bandwidth per frame. However, that algorithm requires a separate special-purpose network for pixel merging. In this paper we present and analyze an expected-case log (d/sup -/)A algorithm for pixel merging that uses network broadcast, and we discuss the algorithm's applicability to shared-memory bus architectures.
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Citations
A sorting classification of parallel rendering
TL;DR: A classification scheme is described that is based on where the sort from object coordinates to screen coordinates occurs, which it is believed is fundamental whenever both geometry processing and rasterization are performed in parallel.
A sorting classification of parallel rendering
Steven Molnar,Michael Cox,David S. Ellsworth,Henry Fuchs +3 more
- 10 Dec 2008
TL;DR: In this article, the authors describe a classification scheme that provides a more structured framework for reasoning about parallel rendering, based on where the sort from object coordinates to screen coordinates occurs, which is fundamental whenever both geometry processing and rasterization are performed in parallel.
456
Graphics for the masses: a hardware rasterization architecture for mobile phones
Tomas Akenine-Möller,Jacob Ström +1 more
- 01 Jul 2003
TL;DR: This work proposes a new hardware architecture for rasterizing textured triangles that focuses on saving memory bandwidth, since an external memory access typically is one of the most energy-consuming operations, and because mobile phones need to use as little power as possible.
166
Patent
Hardware-assisted z-pyramid creation for host-based occlusion culling
Edward Colton Greene
- 09 Mar 2001
TL;DR: In this paper, the authors describe a hierarchical z-buffer system that enables the host processor to perform visibility tests that cull occluded bounding boxes or portals, thereby accelerating rendering by reducing the number of primitives that need to be sent to graphics hardware.
75
Graphics for the masses
Akenine-MöllerTomas,StrömJacob +1 more
TL;DR: The mobile phone is one of the most widespread devices with rendering capabilities, but those capabilities have been very limited because the resources on such devices are extremely scarce; small resources are very scarce.
72
References
•Book
Computer Architecture: A Quantitative Approach
John L. Hennessy,David A. Patterson +1 more
- 01 Dec 1989
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
12.6K
•Book
The Algorithmic Beauty of Plants
Przemyslaw Prusinkiewicz,Aristid Lindenmayer +1 more
- 01 Jan 1990
TL;DR: Graphical modeling using L-systems and turtle interpretation of symbols for plant models and iterated function systems, and Fractal properties of plants.
Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memories
Henry Fuchs,John S. Poulton,John Eyles,Trey Greer,Jack Goldfeather,David S. Ellsworth,Steve Molnar,Greg Turk,Brice Tebbs,Laura Israel +9 more
- 01 Jul 1989
TL;DR: The architecture and initial algorithms for Pixel-Planes 5, a heterogeneous multi-computer designed both for high-speed polygon and sphere rendering and for supporting algorithm and application research in interactive 3D graphics are introduced.
440
PixelFlow: high-speed rendering using image composition
Steven Molnar,John Eyles,John W. Poulton +2 more
- 01 Jul 1992
TL;DR: PixelFlow is described, an architecture for high-speed image generation that overcomes the transformation and frame-buffer– access bottlenecks of conventional hardware rendering architectures and performs antialiasing by supersampling.
High-performance polygon rendering
Kurt Akeley,Tom Jermoluk +1 more
- 01 Jun 1988
TL;DR: A system architecture for realtime display of shaded polygons that heavily leverages parallelism in several forms: pipeline, vector, and array processing, which is unique in providing efficient and balanced graphics that support interactive design and manipulation of solid models.
202