Perturb and simplify: multi-level boolean network optimizer
Shih-Chieh Chang,Malgorzata Marek-Sadowska +1 more
- 06 Nov 1994
- pp 2-5
TL;DR: This paper proposes several new ways in which one or more redundant gates or wires can be added to a network and addresses the problem of efficient redundancy computation which allows to eliminate many unnecessary redundancy tests.
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Abstract: In this paper, we discuss the problem of optimizing a multi-level logic combinational Boolean network. Our techniques apply a sequence of local perturbations and modifications of the network which are guided by the automatic test pattern generation ATPG based reasoning. In particular, we propose several new ways in which one or more redundant gates or wires can be added to a network. We show how to identify gates which are good candidates for local functionality change. Furthermore, we discuss the problem of adding and removing two wires, none of which alone is redundant, but when jointly added/removed they do not affect functionality of the network. We also address the problem of efficient redundancy computation which allows to eliminate many unnecessary redundancy tests. We have performed experiments on MCNC benchmarks and compared the results to those of misII and RAMBO. Experimental results are very encouraging.
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Citations
Majority-Inverter Graph: A New Paradigm for Logic Optimization
TL;DR: This paper proposes a paradigm shift in representing and optimizing logic by using only majority (MAJ) and inversion (INV) functions as basic operations, and develops powerful Boolean methods exploiting global properties of MIGs, such as bit-error masking.
Perturb and simplify: multilevel Boolean network optimizer
TL;DR: This paper presents logic optimization techniques for multilevel combinational networks which apply a sequence of perturbations which result in simplification of the circuit through wires/gates addition and removal which are guided by the ATPG based reasoning.
143
Logic Synthesis for Engineering Change
Chih-Chang Lin,Kuang-Chien Chen,Shih-Chieh Chang,Malgorzata Marek-Sadowska,Kwang-Ting Cheng +4 more
- 01 Jan 1995
TL;DR: Given a synthesized network, the algorithm modifies it minimally to realize a new specification to ensure a large part of engineering effort can be preserved.
89
Circuit optimization by rewiring
TL;DR: This work presents a very efficient optimization method suitable for multi-level combinational circuits based on incremental restructuring of a circuit through a sequence of additions and removals of redundant wires to eliminate unnecessary wire redundancy checking.
77
Physical planning with retiming
Jason Cong,Sung Kyu Lim +1 more
- 05 Nov 2000
TL;DR: A unified approach to partitioning, floorplanning, and retiming for effective and efficient performance optimization is proposed and GEO obtains 35% and 23% better delay results while maintaining comparable cutsize, wirelength, and runtime results.
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