Proceedings Article10.1145/157485.164658
Performance-Driven Steiner Tree Algorithms for Global Routing
Xianlong Hong,Tianxiong Xue,Ernest S. Kuh,Chung-Kuan Cheng,Jin Huang +4 more
- 01 Jul 1993
- pp 177-181
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TL;DR: Two performance-driven Steiner tree algorithms for global routing are presented which consider the minimization of timing delay during the tree construction as the goal and are based on nonlinear optimization method and heuristic approach.
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Abstract: This paper presents two performance-driven Steiner tree algorithms for global routing which consider the minimization of timing delay during the tree construction as the goal One algorithm is based on nonlinear optimization method, another uses heuristic approach to guide the construction of Steiner tree A new timing model is established which includes both total length and critical path between source and sink in delay formulation, and an upper bound for timing delay is deducted and used to guide both algorithms Experiment results are given to demonstrate the effectiveness of the two algorithms
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Citations
Performance optimization of VLSI interconnect layout
TL;DR: A comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for high-performance V LSI circuit design under the deep submicron fabrication technologies.
333
Optimal wiresizing under Elmore delay model
Jason Cong,Kwok-Shing Leung +1 more
TL;DR: A polynomial-time optimal wiresizing algorithm for arbitrary interconnect tree structures under Elmore delay model is developed that reduces interconnect delay by up to 51% when compared to the uniform-width solution of the same routing topology.
131
Simultaneous driver and wire sizing for performance and power optimization
Jason Cong,Cheng-Kok Koh +1 more
TL;DR: This paper studies the simultaneous driver and wire sizing problem under two objective functions: i) delay minimization only, or ii) combined delay and power dissipation minimization, and implements polynomial time algorithms and efficient algorithms for computing optimal SDWS solutions under the two objectives.
122
Patent
Method and apparatus for routing
Steven Teig,Jonathan Frankle,Etienne Jacques,Andrew Caldwell +3 more
- 31 Dec 2002
TL;DR: In this paper, the shape of interconnect-line ends is dynamically defined on a particular layer based on the routing directions available on the particular layer to improve the alignment of route segments that have differing widths.
93
Patent
Routing method and apparatus
Steven Teig,Oscar Buset,Andrew Caldwell,Etienne Jacques,Jonathan Frankle,Heng-Yi Chao +5 more
- 05 Jan 2002
TL;DR: In this paper, the authors proposed a routing method that uses diagonal routes to route several nets within a region of a circuit layout, each net includes a set of pins in the region, and then identifies a route that connects the sub-regions that contain a pin from the set of nets of the particular net.
79
References
The steiner problem in graphs
Stuart E. Dreyfus,R. A. Wagner +1 more
TL;DR: An algorithm for solving the Steiner problem on a finite undirected graph is presented, which computes the set of graph arcs of minimum total length needed to connect a specified set of k graph nodes.
821
Approximation of wiring delay in MOSFET LSI
TL;DR: Two approximation methods for wiring delay in MOS LSI are studied and the widely used L ladder circuit model is found to be a poor approximation, while /spl pi and T ladder circuit models give satisfactory results.
423
Provably good performance-driven global routing
TL;DR: A provably good performance-driven global routing algorithm for both cell-based and building-block design based on a new bounded-radius minimum routing tree formulation, based on an analog of Prim's minimum spanning tree construction.
RITUAL: a performance driven placement algorithm for small cell ICs
Arvind Srinivasan,Kamal Chaudhary,Ernest S. Kuh +2 more
- 11 Nov 1991
TL;DR: An efficient algorithm, RITUAL (residual iterative technique for updating all Lagrange multipliers), for obtaining a placement of cell-based ICs subject to performance constraints is described and yields very good results, as is shown on a set of real examples.
119
A global router using an efficient approximate multicommodity multiterminal flow algorithm
Robert Clinton Carden,Chung-Kuan Cheng +1 more
- 01 Jun 1991
TL;DR: This work shows that under certain conditions, an epsilon bound 2-terminal multicommodity flow algorithm with fractional flows is adapted to handle multiterminal commodities and derives an approximate optimal solution.
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