Open AccessProceedings Article10.1109/ASPDAC.1995.486234

Performance driven multiple-source bus synthesis using buffer insertion

- 06 Aug 2002

- pp 273-278

TL;DR: In this paper, a heuristic algorithm for a given topology of a multiple source and multiple sink bus to reduce the signal delay time is proposed, which minimizes the delay by inserting buffers into the candidate locations and sizing the buffers.

Abstract: A heuristic algorithm for a given topology of a multiple source and multiple sink bus to reduce the signal delay time is proposed. The algorithm minimizes the delay by inserting buffers into the candidate locations and sizing the buffers. Experiments show up to 7.2 %, 20.7 %, and 29.6 % improvement in delay for 2.0, 0.5, and 0.3 micron technologies, respectively.

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1. What are the contributions in "Performance driven multiple-source bus synthesis using buffer insertion" ?

In this paper, the authors proposed a buffer insertion algorithm for a given topology of a multiple-source and multiple-sink bus to reduce the signal delay.

2. What have the authors stated for future works in "Performance driven multiple-source bus synthesis using buffer insertion" ?

Future work includes area limitation and power consumption.

Fig. 7 shows the comparison for Case 5 for 0.5m technology. The x-axis represents the percentage of the core size with respect to the original core size. From the figure, we observe that the delay time with the buffer insertion is reduced as the core size shrinks.

Fig. 1: An example of a bus with six terminals.

Fig. 2: A multiple-source bus with buffer insertion.

Fig. 4: (a) A buffer model and (b) the equivalent delay model.

Fig. 5: Curve variation of the delay timeaij

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1.7K

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Sparse matrix technology

Sergio Pissanetzky

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TILOS: A posynomial programming approach to transistor sizing

John P. Fishburn, +1 more

- 01 Jan 2003

TL;DR: A new transistor sizing algorithm, which couples synchronous timing analysis with convex optimization techniques, is presented, which shows that any point found to be locally optimal is certain to be globally optimal.

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Proceedings Article•10.1109/ISCAS.1990.112223

Buffer placement in distributed RC-tree networks for minimal Elmore delay

L.P.P.P. van Ginneken

- 01 May 1990

TL;DR: An algorithm is presented for choosing the buffer positions for a wiring tree such that the Elmore delay is minimal, and an extension of the basic algorithm allows minimization of the number of buffers as a secondary objective.

...read moreread less

543

Performance driven multiple-source bus synthesis using buffer insertion

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1. What are the contributions in "Performance driven multiple-source bus synthesis using buffer insertion" ?

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References

An Effective Heuristic Algorithm for the Traveling-Salesman Problem

The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers

Sparse matrix technology

TILOS: A posynomial programming approach to transistor sizing

Buffer placement in distributed RC-tree networks for minimal Elmore delay

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