Parity check matrix

TL;DR: In this paper, the reliability data for a variable node is received at a first and a second time, and reliability values for the variable node are obtained at a second and a third time.

TL;DR: In this paper, a first decoder attempts to decode the data based on a hard decision input for a symbol, and when the attempt of decoding the data with hard decision inputs fails, a request is transmitted reliability information for the symbol.

TL;DR: This lecture presents a probabilistic computation framework for improving the resiliency of logic gates and circuits under random conditions induced by voltage or current fluctuation, and discusses various approaches for noise-resilient logic gate design.

TL;DR: In this article, a low-error floor QC-LDPC (Quasi-Cyclic Low-Density Parity-Check) code construction method using ACE (Approximate Cycle Extrinsic Message Degree) and PS (Partition and Shift).

TL;DR: Simulation results show that the PEG algorithm is a powerful algorithm to generate good short-block-length LDPC codes.

TL;DR: A Viterbi-like algorithm is proposed that selectively avoids small cycle clusters that are isolated from the rest of the graph and yields codes with error floors that are orders of magnitude below those of random codes with very small degradation in capacity-approaching capability.

TL;DR: In this article, a structured parity-check matrix H is proposed, wherein H is an expansion of a base matrix Hb and wherein Hb comprises a section Hb1 and a section hb2, and Hb2 comprises a first part comprising a column hb having an odd weight greater than 2, and a second part comprising matrix elements for row i, column j equal to 1 for i=j, 1 for j+1, and 0 elsewhere.

TL;DR: It is shown that the ML SNR threshold of ARA codes also approaches very closely to that of random codes, and these codes have better interleaving gain than turbo codes.