Open Access
Parallelizing Compiler Techniques Based on Linear Inequalities
Saman Amarasinghe
- 01 Jan 1997
TL;DR: The Stanford SUIF interprocedural parallelizer is capable of detecting coarser granularity of parallelism in sequential scientific applications than previously possible and a framework based on systems of linear inequalities for developing compiler algorithms is introduced.
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Abstract: Shared-memory multiprocessors, built out of the latest microprocessors, are becoming a widely available class of computationally powerful machines. These affordable multiprocessors can potentially deliver supercomputer-like performance to the general public.
To effectively harness the power of these machines it is important to find all the available parallelism in programs. The Stanford SUIF interprocedural parallelizer we have developed is capable of detecting coarser granularity of parallelism in sequential scientific applications than previously possible. Specifically, it can parallelize loops that span numerous procedures and hundreds of lines of codes, frequently requiring modifications to array data structures such as array privatization. Measurements from several standard benchmark suites demonstrate that aggressive interprocedural analyses can substantially advance the capability of automatic parallelization technology.
However, locating parallelism is not sufficient in achieving high performance. It is critical to make effective use of the memory hierarchy. In parallel applications, false sharing and cache conflicts between processors can significantly reduce performance. We have developed the first compiler that automatically performs a full suite of data transformations (a combination of transposing, strip-mining and padding). The performance of many benchmarks improves drastically after the data transformations.
We introduce a framework based on systems of linear inequalities for developing compiler algorithms. Many of the whole program analyses and aggressive optimizations in our compiler employ this framework. Using this framework general solutions to many compiler problems can be found systematically.
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Citations
Exploiting superword level parallelism with multimedia instruction sets
Samuel Larsen,Saman Amarasinghe +1 more
- 01 May 2000
TL;DR: This paper has developed a simple and robust compiler for detecting SLPP that targets basic blocks rather than loop nests, and is able to exploit parallelism both across loop iterations and within basic blocks.
Generation of Efficient Nested Loops from Polyhedra
TL;DR: This work presents a general parameterized method for code generation based on dual representation of polyhedra that uses a simple recursion on the dimensions of the domains, and enables fine control over the tradeoff between code size and control overhead.
243
SUIF Explorer: an interactive and interprocedural parallelizer
Shih-Wei Liao,Amer Diwan,R. Bosch,Anwar Ghuloum,Monica S. Lam +4 more
- 01 May 1999
TL;DR: The SUIF Explorer as mentioned in this paper is an interactive parallelization tool that is more effective than previous systems in minimizing the number of lines of code that require programmer assistance by using dynamic execution analyzers to identify those important loops that are likely to be parallelizable.
173
Bottlenecks in multimedia processing with SIMD style extensions and architectural enhancements
TL;DR: The MediaBreeze architecture is proposed, which uses hardware support for efficient address generation, looping, and data reorganization (permute, packing/unpacking, transpose, etc.) and provides a better performance than a 16-way processor with current SIMD extensions.
Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors
Qingda Lu,Christophe Alias,Uday Bondhugula,Thomas Henretty,Sriram Krishnamoorthy,J. Ramanujam,Atanas Rountev,P. Sadayappan,Yongjian Chen,Haibo Lin,Tin-Fook Ngai +10 more
- 12 Sep 2009
TL;DR: This paper develops a compile-time framework for data locality optimization via data layout transformation using a polyhedral model and demonstrates the effectiveness of the approach on a 16-core 2D tiled CMP.
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