Proceedings Article10.1109/SIPS.2010.5624783
Parallel high throughput soft-output sphere decoder
Q. Qi,Chaitali Chakrabarti +1 more
- 09 Nov 2010
- pp 174-179
TL;DR: A high throughput soft-output fixed complexity sphere decoder that is parallel and has comparable performance to list fixed complexity spheres decoder (LFSD), and a low complexity LLR algorithm to allow parallel update of LLR values is proposed.
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Abstract: Multiple-Input-Multiple-Output communication systems demand fast sphere decoding with high performance. We propose a high throughput soft-output fixed complexity sphere decoder (PFSD) that is parallel and has comparable performance to list fixed complexity sphere decoder (LFSD) and K-best sphere decoder. In addition, we propose a parallel QR decomposition algorithm to lower the preprocessing overhead, and a low complexity LLR algorithm to allow parallel update of LLR values. We demonstrate the BER and computation complexity advantages of the PFSD algorithm in a 4×4 16-QAM system. The PFSD algorithm has been mapped onto Xilinx XC4VLX160 FPGA. The resulting PFSD decoder can produce 8 candidate vectors per clock cycle, and achieve upto 75Mbps throughput for 4×4 64-QAM configuration at 100MHz with low control overhead.
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Citations
Real-Valued Fixed-Complexity Sphere Decoder for High Dimensional QAM-MIMO Systems
TL;DR: The new real-valued fixed-complexity sphere decoder (RFSD) algorithm derived achieves similar quasi-ML decoding performance as FSD, but with an average 70% reduction in computational complexity, as it demonstrates from both theoretical and implementation perspectives for quadrature amplitude modulation (QAM)-MIMO systems.
42
Software-Defined Sphere Decoding for FPGA-Based MIMO Detection
Xuezheng Chu,John McAllister +1 more
TL;DR: A series of unique SD implementations are presented, culminating in the only single-chip, real-time quasi-optimal SD for 4 × 4 16-QAM 802.11n MIMO, demonstrating that the high performance software-defined architectures which enable these implementations exhibit cost comparable to dedicated circuit architectures.
32
An Efficient Fault-Tolerance Design for Integer Parallel Matrix–Vector Multiplications
TL;DR: Field-programmable gate array evaluation shows that the proposed scheme can significantly reduce the overheads compared to the protection of each MVM on its own, therefore, the proposed technique can be used to reduce the cost of providing fault tolerance in practical implementations.
8
Flexible N-Way MIMO Detector on GPU
Michael Wu,Bei Yin,Joseph R. Cavallaro +2 more
- 17 Oct 2012
TL;DR: It is shown that this flexible detector, including QR decomposition preprocessing, outperforms existing GPU MIMO detectors while maintaining good bit error rate (BER) performance.
GPU Acceleration of a Configurable N-Way MIMO Detector for Wireless Systems
Michael Wu,Bei Yin,Guohui Wang,Christoph Studer,Joseph R. Cavallaro +4 more
- 01 Aug 2014
TL;DR: A flexible N-Way MIMO detector that achieves excellent error-rate performance and high throughput on graphics processing units (GPUs) and exploits the massive parallelism available in GPUs.
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