Parallel exponentiators using data signal processor chips and transputers for a flexible and efficient software implementation of public-key cryptosystems to run on PC's or larger systems

TL;DR: This proposal gives two efficient and flexible solutions to improve exponentiation which is at the heart of public-key cryptosystems (Diffie-Hellman, Rivest-Shamir-Adleman (R.S.P.A.), El Gamal or Data Security Pipe Protocol (D.P.) schemes).

Abstract: Algorithms for parallel computation (multiplication, reduction and exponentiation) over finite fields in the general case: GF(N) and where N is a Mersenne prime of 127, 521, 607 or 1279 bits: GF(2P-1) are described. They find a direct application in the generation of asymmetric public-key cryptosystems.Two different ways are suggested to implement efficiently these algorithms:The first takes advantage of the RISC architecture of the transputers (INMOS IMS T414), the parallelism of the algorithms, the 64-bit long integer type available in Occam 2 and the Karatsuba algorithm to optimize the integer multiplication.The second suggests the design of an exponentiator board where mb banks of 512 bits are used in parallel for multiplication while mb others are used for squaring. Each of these banks is supposed to be a Data Signal Processor (DSP) chip (INMOS IMS A100) which is composed of 32 cascadable 16 x 16-bit Multipliers-Accumulators (MAC's).As an example:An exponentiation process programmed in Fortran 77 and run on a PC-AT at 8 Mz could increase its velocity by a factor > 500 in the first described way which could be estimated to be much better in the second, while using a 521-bit modulus and a PC as an host machine.This proposal gives two efficient and flexible solutions to improve exponentiation which is at the heart of public-key cryptosystems (Diffie-Hellman, Rivest-Shamir-Adleman (R.S.A.), El Gamal or Data Security Pipe Protocol (D.S.P.P.) schemes).