Proceedings Article10.1109/ESSCIRC.2008.4681832
Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs
R. Naseer,Jeffrey Draper +1 more
- 18 Nov 2008
- pp 222-225
159
TL;DR: A double-error correcting ECC implementation technique suitable for SRAM applications is presented and shows that this DEC scheme reduces errors by 98.5% compared to only 44% reduction by conventional SEC-DED ECC.
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Abstract: The range of SRAM multi-bit upsets (MBU) in sub-100 nm technologies is characterized using irradiation tests on two prototype ICs, developed in 90 nm commercial processes. Results reveal that MBU, as large as 13-bit, can occur in these technologies, limiting the efficacy of conventional SEC-DED error-correcting codes (ECC). A double-error correcting (DEC) ECC implementation technique suitable for SRAM applications is presented. Results show that this DEC scheme reduces errors by 98.5% compared to only 44% reduction by conventional SEC-DED ECC.
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Citations
Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology
TL;DR: A novel radiation-hardened-by-design 12T memory cell is proposed to tolerate single node upset and multiple-node upset based on upset physical mechanism behind soft errors together with reasonable layout-topology.
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A New SEC-DED Error Correction Code Subclass for Adjacent MBU Tolerance in Embedded Memory
Adam Neale,Manoj Sachdev +1 more
TL;DR: A new ECC scheme is introduced that provides not only the basic SEC-DED coverage but also both DAEC and scalable adjacent error detection ( xAED) with a reduction in miscorrection probability as well.
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Young Hoon Son,Suk-Han Lee,Seongil O,Sanghyuk Kwon,Nam Sung Kim,Jung Ho Ahn +5 more
- 09 Mar 2015
TL;DR: CiDRA is proposed, a cache-inspired DRAM resilience architecture, which substantially reduces the area and latency overheads of correcting bit errors on random locations due to these faulty cells.
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Adjacent-MBU-Tolerant SEC-DED-TAEC-yAED Codes for Embedded SRAMs
TL;DR: A set of double adjacent error correction (DAEC) codes is modified to provide triple adjacent error Correction for a cost of zero additional check-bits over the code's DAEC equivalent, yielding a 2.25× reduction in bit-level soft error rate for a 22-nm MBU error channel model.
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DIRT latch: A novel low cost double node upset tolerant latch
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