Patent
Optional virtual memory system
Kenneth J. Thurber,Jon C. Strauss +1 more
- 16 Dec 1976
45
TL;DR: In this paper, the address generation function in the memory addressing mechanism has been separated into two distinct parts, address computation and address translation, and the hardware components in the address translation part can be changed at any time.
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Abstract: The present invention relates to a memory addressing mechanism which has been formulated to accommodate three address structures: real, based and virtual. To accomplish this result the address generation function in the memory addressing mechanism has been separated into two distinct parts, address computation and address translation. By merely changing the hardware components in the address translation part of the memory addressing mechanism and leaving the hardware in the address computation part constant, an optional memory addressing mechanism which supports either a real address structure, a based address structure or a virtual address structure can be implemented. Further, the present invention with the virtual address translation apparatus in cooperation with the fixed address computation apparatus provides a virtual addressing mechanism which will compute and retrieve a memory word utilizing a four-segment memory address with only two memory references.
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Citations
Patent
Extended address generating apparatus and method
Blaine D. Gaither,William Wallace Farley,Albert Johnson,Brian Leslie Parker +3 more
- 14 Apr 1982
TL;DR: In this article, selective indexed addressing is employed for providing index data, which is also used for deriving variable dimension override data, and the derived dimension override value is used to selectively access an address locating entry in a table of entries corresponding to the applicable program.
207
Patent
Method and operating system for executing programs in a multi-mode microprocessor
James G. Letwin
- 09 Apr 1986
TL;DR: In this article, the authors present a mode switching method for multi-mode operating systems using Intel 80286 microprocessors, including means for storing the operating system routines to maximize performance of the system in real mode.
190
Patent
Virtual memory address translation mechanism with controlled data persistence
Albert Chang,John Cocke,Mark F. Mergen,George Radin +3 more
- 30 Dec 1982
TL;DR: In this paper, a translation look-Aside buffer (TLB) is used to translate frequently used virtual addresses into real addresses, where the TLBs are addressed using a subset of the effective address whereupon the contents of the addressed TLB are examined for a match with the effective addresses.
130
Patent
Apparatus and method for providing private and shared access to host address and data spaces by guest programs in a virtual machine computer system
David P. Brelsford,Melvin M. Cutler,Jean Louis Lafitte,Joseph Martin Gdaniec,Damian L. Osisek,Kenneth Ernest Plambeck +5 more
- 02 Oct 1990
TL;DR: In this paper, a method and apparatus for providing common access to data spaces by a plurality of virtual machine guests emulated on a host computer system is presented, where a token received from a given one of the virtual machine guest is used to identify a particular host data space.
124
Patent
Paged memory management unit capable of selectively supporting multiple address spaces.
William C. Moyer,Michael W. Cruess,William M. Keshlear,John Zolnowsky +3 more
- 06 Nov 1986
TL;DR: In this paper, a paged memory management unit (PMMU) is adapted to selectively access a plurality of pointer tables and page tables stored in a memory to translate a selected logical address (LA) into a corresponding physical address (PA) by first combining a first portion of the logical address and a first table pointer to access a first one of the pointer tables (PT) to obtain therefrom a page table pointer.
71
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Patent
Virtual memory system
Andrew Peter Maund,John Walter Neave,Neil Francis Trevett,Simon James Moore,Malcolm Eric Wilson +4 more
- 17 Oct 1972
TL;DR: In this paper, the authors describe a virtual memory system comprising a main storage and a smaller high speed buffer, which is real-address oriented, where current virtual-to-real address translations are retained in a Translation Look Aside Table (TLAT) and real addresses of data stored in the buffer are maintained in a buffer directory.
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Forrest Arthur Reiley,James Theodore Richcreek +1 more
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TL;DR: In this paper, a data processing system includes a central processing unit which uses virtual addressing in address control words to access a high speed buffer store of limited storage capacity and simultaneously to access the high capacity main store of slower operating speed, whereby no time is lost in accessing the main store in the event the buffer store cannot be accessed.
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Patent
Data input and output controller
Jacques Michel Jean Bienvenu,Jean-Claude Marcel Cassonnet,Marc Appell +2 more
- 28 Oct 1975
TL;DR: In this article, an input/output controller for an information processing system comprising a main memory, a central processing unit, a peripheral controller and a plurality of peripheral units coupled to the central processing units is disclosed.
56
Patent
Storage control and address translation
R Ross
- 23 Dec 1971
TL;DR: In this article, a virtual memory system comprising a main storage and a smaller high speed buffer is described, where current virtual-to-real address translations are retained in a Storage Control and Address Translator (SCAT).
48
Patent
Data processing system memory relocation apparatus and method
John Cocke,David Robert Helman +1 more
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TL;DR: In this article, a branch instruction includes an indicator as to whether the branch address is a physical address on the same or another page or a virtual address on another page, which can be used to load the page if necessary.
25
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