Optimizing designs containing black boxes
TL;DR: A notion of equivalence is established for gate-level netlists containing black boxes, and a procedure is introduced that computes the complete don't care set and can achieve more minimization than conventional synthesis.
read more
Abstract: We are concerned with optimizing gate-level netlists containing “black boxes,” that is, components whose functionality is not available to the optimization tool. We establish a notion of equivalence for gate-level netlists containing black boxes, and prove that it is sound and complete. We show that conventional approaches to optimizing such netlists fail to fully exploit the don't care flexibility available for synthesis. Based on our new notion of equivalence, we introduce a procedure that computes the complete don't care set. Experiments indicate that our procedure can achieve more minimization than conventional synthesis.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
A theory of nondeterministic networks
TL;DR: It is shown that an ND network's behavior can be classified into at least three types, all of which coalesce when the network becomes deterministic, and proved that all three types can be used in a hierarchical-synthesis paradigm.
6
Patent
System and method for improved logic simulation using a negative unknown boolean state
Richard Nicholas
- 14 Sep 2006
TL;DR: In this article, a system and method for simulating a circuit design using both an unknown Boolean state and a negative unknown boolean state is provided, where one or more initial simulated logic elements are initialized to the unknown Boolean states.
5
Patent
Structure for improved logic simulation using a negative unknown boolean state
Richard Nicholas
- 15 Aug 2008
TL;DR: In this article, a system and method for simulating a circuit design using both an unknown Boolean state and a negative unknown boolean state is provided, where one or more initial simulated logic elements are initialized to the unknown Boolean states.
2
Efficient pattern-based verification of connections to IP cores
Ilia Polian,Wolfgang Günther,Bernd Becker +2 more
- 19 Nov 2001
TL;DR: This work proposes a method that is based on test patterns, using only those patterns for simulation, that in almost all cases 100% of the errors can be detected in verification of IP cores.
1
References
Graph-Based Algorithms for Boolean Function Manipulation
TL;DR: In this paper, the authors present a data structure for representing Boolean functions and an associated set of manipulation algorithms, which have time complexity proportional to the sizes of the graphs being operated on, and hence are quite efficient as long as the graphs do not grow too large.
The maximum set of permissible behaviors for FSM networks
Yosinori Watanabe,Robert K. Brayton +1 more
- 07 Nov 1993
TL;DR: It is shown that the complete set of permissible behaviors can be computed and represented by a single non-deterministic finite state machine, called the E-machine, and the transition relation of theE-machine is obtained by a fixed point computation.
45
Observability relations and observability don't cares
Hamid Savoj,Robert K. Brayton +1 more
- 11 Nov 1991
TL;DR: It is shown that the observability don't cares (ODCs) for a node y/sub i/ in N' provide the maximum flexibility for implementing y/ Sub i/ and subsume the flexibility obtained for y/ sub i/in N even withDon't cares provided at each output.
40
Optimizing designs containing black boxes
Tai-Hung Liu,Khurram Sajid,Adnam Aziz,Vigyan Singhal +3 more
- 13 Jun 1997
TL;DR: A sound and complete methodology for optimizing designs containing black boxes i.e., components whose functionality is not known and which arise naturally in the course of hierarchical design.
Logic optimization with multi-output gates
Y. Watanabe,L. Guerra,Robert K. Brayton +2 more
- 03 Oct 1993
TL;DR: This paper provides a procedure for computing a maximally-compatible set of permissible relations for multiple-output gates and proposes a heuristic for clustering single- Output gates into multi- output gates, so that increased concurrent optimization can be obtained.
11