Optimization Techniques for GPU Programming
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TL;DR: In this article , a survey discusses various optimization techniques found in 450 articles published in the last 14 years and analyzes the optimizations from different perspectives which shows that the various optimizations are highly interrelated, explaining the need for techniques such as auto-tuning.
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Abstract: In the past decade, Graphics Processing Units have played an important role in the field of high-performance computing and they still advance new fields such as IoT, autonomous vehicles, and exascale computing. It is therefore important to understand how to extract performance from these processors, something that is not trivial. This survey discusses various optimization techniques found in 450 articles published in the last 14 years. We analyze the optimizations from different perspectives which shows that the various optimizations are highly interrelated, explaining the need for techniques such as auto-tuning.
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References
Efficient sparse matrix-vector multiplication on GPUs using the CSR storage format
Joseph L. Greathouse,Mayank Daga +1 more
- 16 Nov 2014
TL;DR: This work proposes a novel algorithm, CSR-Adaptive, which keeps the CSR format intact and maps well to GPUs, and achieves an average speedup of 14.7× over existingCSR-based algorithms and 2.3× over clSpMV cocktail, which uses an assortment of matrix formats.
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Reducing branch divergence in GPU programs
Tianyi David Han,Tarek S. Abdelrahman +1 more
- 05 Mar 2011
TL;DR: This work proposes two novel software-based optimizations, called iteration delaying and branch distribution that aim to reduce branch divergence, and shows that they improve the performance of the synthetic benchmarks and that of the real-world application by 12% and 16% respectively.
Exploiting Memory Access Patterns to Improve Memory Performance in Data-Parallel Architectures
TL;DR: Techniques for enhancing the memory efficiency of applications on data-parallel architectures are presented, based on the analysis and characterization of memory access patterns in loop bodies; they target vectorization via data transformation to benefit vector-based architectures and algorithmic memory selection for scalar- based architectures.
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Thread block compaction for efficient SIMT control flow
Wilson W. L. Fung,Tor M. Aamodt +1 more
- 12 Feb 2011
TL;DR: This paper proposes and evaluates the benefits of extending the sharing of resources in a block of warps, already used for scratchpad memory, to exploit control flow locality among threads, and shows that this compaction mechanism provides an average speedup of 22% over a baseline per-warp, stack-based reconvergence mechanism.
High performance and scalable radix sorting: a case study of implementing dynamic parallelism for gpu computing
Duane Merrill,Andrew S. Grimshaw +1 more
TL;DR: A family of very efficient parallel algorithms for radix sorting; and the authors' allocation-oriented algorithmic design strategies that match the strengths of GPU processor architecture to this genre of dynamic parallelism are presented.
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