Optimization Techniques for GPU Programming
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TL;DR: In this article , a survey discusses various optimization techniques found in 450 articles published in the last 14 years and analyzes the optimizations from different perspectives which shows that the various optimizations are highly interrelated, explaining the need for techniques such as auto-tuning.
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Abstract: In the past decade, Graphics Processing Units have played an important role in the field of high-performance computing and they still advance new fields such as IoT, autonomous vehicles, and exascale computing. It is therefore important to understand how to extract performance from these processors, something that is not trivial. This survey discusses various optimization techniques found in 450 articles published in the last 14 years. We analyze the optimizations from different perspectives which shows that the various optimizations are highly interrelated, explaining the need for techniques such as auto-tuning.
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References
A high-performance matrix---matrix multiplication methodology for CPU and GPU architectures
TL;DR: An MMM methodology is presented where the optimum scheduling parameters are found by decreasing the search space theoretically, while the major scheduling sub-problems are addressed together as one problem and not separately according to the hardware architecture parameters and input size.
Layup: Layer-adaptive and Multi-type Intermediate-oriented Memory Optimization for GPU-based CNNs
TL;DR: A fast layer-type-specific method for memory optimization is presented, based on the new finding that a single memory optimization often shows dramatic differences in time performance for different types of layers, and a new memory reuse method is presented in which greater attention is paid to multi-type intermediate data.
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Optimization and performance evaluation of the IDR iterative Krylov solver on GPUs
Hartwig Anzt,Moritz Kreutzer,Eduardo Ponce,Gregory D. Peterson,Gerhard Wellein,Jack Dongarra,Jack Dongarra,Jack Dongarra +7 more
TL;DR: An optimized GPU implementation for the induced dimension reduction algorithm is presented, which improves data locality, combines it with an efficient sparse matrix vector kernel, and investigates the potential of overlapping computation with communication as well as the possibility of concurrent kernel execution.
On the Development of Variable Size Batched Computation for Heterogeneous Parallel Architectures
Ahmad Abdelfattah,Azzam Haidar,Stanimire Tomov,Jack Dongarra +3 more
- 23 May 2016
TL;DR: This paper proposes a foundation for high performance variable-size batched matrix computation based on Graphics Processing Units (GPUs) and proposes new interfaces and mechanisms to handle the irregular computation pattern on the GPU.
On the GPU Performance of 3D Stencil Computations Implemented in OpenCL
Huayou Su,Huayou Su,Huayou Su,Nan Wu,Nan Wu,Mei Wen,Chunyuan Zhang,Xing Cai,Xing Cai +8 more
- 16 Jun 2013
TL;DR: It is found that typical optimization techniques such as array padding, plane sweeping and chunking give similar performance boosts to the OpenCL implementations, as those obtained in corresponding CUDA programs.
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