Optimization Techniques for GPU Programming
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TL;DR: In this article , a survey discusses various optimization techniques found in 450 articles published in the last 14 years and analyzes the optimizations from different perspectives which shows that the various optimizations are highly interrelated, explaining the need for techniques such as auto-tuning.
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Abstract: In the past decade, Graphics Processing Units have played an important role in the field of high-performance computing and they still advance new fields such as IoT, autonomous vehicles, and exascale computing. It is therefore important to understand how to extract performance from these processors, something that is not trivial. This survey discusses various optimization techniques found in 450 articles published in the last 14 years. We analyze the optimizations from different perspectives which shows that the various optimizations are highly interrelated, explaining the need for techniques such as auto-tuning.
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References
Systematic adaptation of stencil‐based 3D MPDATA to GPU architectures
TL;DR: The presented methods of the MPDATA adaptation to GPU architectures allow us to efficiently use many graphics processors within a single node by applying peer‐to‐peer data transfers between GPU global memories.
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Terabit encryption in a second: Performance evaluation of block ciphers in GPU with Kepler, Maxwell, and Pascal architectures
TL;DR: The feasibility of the GPU as an accelerator to perform high‐speed encryption in server environments is investigated and optimized implementations of a conventional block cipher (AES) and new lightweight block ciphers (LEA, Chaskey, SIMON, SPECK, and SIMECK) across three new GPU architectures (Kepler, Maxwell, and Pascal).
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Performance Tuning and Optimization Techniques of Fixed and Variable Size Batched Cholesky Factorization on GPUs
Ahmad Abdelfattah,Azzam Haidar,Stanimire Tomov,Jack Dongarra +3 more
- 01 Jun 2016
TL;DR: This paper presents a high performance batched Cholesky factorization on large sets of relatively small matrices using Graphics Processing Units (GPUs), and addresses both fixed and variable size batched problems.
Scale-Free Sparse Matrix-Vector Multiplication on Many-Core Architectures
TL;DR: This paper proposes a hardware oblivious implementation for heterogeneous many-core processors using OpenCL using a novel SpMV format called hybrid COO+CSR (HCC), which employs 2-D jagged partitioning to balance the workload among a large number of cores and improve the data locality.
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Eliminating Intra-Warp Load Imbalance in Irregular Nested Patterns via Collaborative Task Engagement
Farzad Khorasani,Bryan Rowe,Rajiv Gupta,Laxmi N. Bhuyan +3 more
- 23 May 2016
TL;DR: A novel software technique called Collaborative Task Engagement (CTE) is introduced that achieves sustained high warp execution efficiencies across irregular inputs and provides portable performance.
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