Patent
Optimization processing for integrated circuit physical design automation system using chaotic fitness improvement method
Douglas B. Boyle,James S. Koford,Ranko Scepanovic,Edwin R. Jones,Michael D. Rostoker +4 more
- 19 Apr 1994
56
TL;DR: In this paper, the authors propose to use the centroid of the net of cells to which the cell is connected, and then move the cell toward this centroid by a distance that is equal to the distance from the current position of the cell to the center of the network, multiplied by a "chaos" factor.
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Abstract: The fitness of a cell placement for an integrated circuit chip is optimized by relocating at least some of cells to new locations that provide lower interconnect congestion. For each cell, the centroid of the net of cells to which the cell is connected is computed. The cell is then moved toward the centroid by a distance that is equal to the distance from the current position of the cell to the centroid multiplied by a "chaos" factor λ. The value of λ is selected such that the cell relocation operations will cause the placement to converge toward an optimal configuration without chaotic diversion, but with a sufficiently high chaotic element to prevent the optimization operation from becoming stuck at local fitness maxima. The new cell locations can be modified to include the effects of cells in other locations, such as by incorporating a function of cell density gradient or force direction into the computation. This spreads out clumps of cells so that the density of cells is more uniform throughout the placement. The attraction between cells in the nets is balanced against repulsion caused by a high local cell density, providing an optimized tradeoff of wirelength, feasibility and congestion.
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Citations
Patent
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- 06 Mar 2001
TL;DR: In this paper, a method for design optimization using logical and physical information is provided, which includes a behavioral description of an integrated circuit or a portion of an Integrated Circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements.
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207
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