Optimality study of resource binding with multi-Vdds
Deming Chen,Jason Cong,Yiping Fan,Junjuan Xu +3 more
- 24 Jul 2006
- pp 580-585
TL;DR: This work presents an optimality study for resource binding targeting designs with multi-Vdds as a min-cost network flow problem, but with special equal-flow constraints, which leads to an easy reduction to the integer linear programming (ILP) solution and also enables efficient approximate solution by Lagrangian relaxation.
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Abstract: Deploying multiple supply voltages (multi-Vdds) on one chip is an important technique to reduce dynamic power consumption. In this work we present an optimality study for resource binding targeting designs with multi-Vdds. This is similar to the voltage-island design concept, except that the granularity of our voltage island is on the functional-unit level as opposed to the core level. We are interested in achieving the maximum number of low-Vdd operations and, in the same time, minimizing switching activity during functional unit binding. To the best of our knowledge, there is no known optimal solution to this problem. To compute an optimal solution for this problem and examine the quality gap between our solution and previous heuristic solutions, we formulate this problem as a min-cost network flow problem, but with special equal-flow constraints. This formulation leads to an easy reduction to the integer linear programming (ILP) solution and also enables efficient approximate solution by Lagrangian relaxation. Experimental results show that the optimal solution computed based on our formulation provides 7% more low-Vdd operations and also reduces the total switching activity by 20% compared to one of the best known heuristic algorithms that consider multi-Vdd assignments only.
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Citations
Impact of FPGA architecture on resource sharing in high-level synthesis
Stefan Hadjis,Andrew Canis,Jason H. Anderson,Jongsok Choi,Kevin Nam,Stephen J. Brown,Tomasz Czajkowski +6 more
- 22 Feb 2012
TL;DR: It is shown that certain multi-operator patterns occur multiple times in programs, creating additional opportunities for sharing larger composite functional units comprised of patterns of interconnected operators.
Resource-Aware Throughput Optimization for High-Level Synthesis
Peng Li,Peng Zhang,Louis-Noël Pouchet,Jason Cong +3 more
- 22 Feb 2015
TL;DR: It is demonstrated that maximizing the throughput of each individual loop is not always the most efficient approach to achieving the maximum system-level throughput, and an algorithm is developed to determine the optimal resource usage and initiation intervals for each loop in the applications to achieve maximum throughput within a given area budget.
Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS design
Mateja Putic,Liang Di,Benton H. Calhoun,John Lach +3 more
- 04 Oct 2009
TL;DR: A circuit/architecture co-design methodology called Panoptic Dynamic Voltage Scaling (PDVS) that makes more efficient use of common circuit structures and algorithm-level processing rate control, allowing efficient dithering among statically scheduled algorithms with sub-block energy savings.
High-level Synthesis for Low-power Design
TL;DR: The recent research development of using HLS to effectively explore a multi-dimensional design space and derive low-power implementations is discussed and potential opportunities in tackling these challenges are outlined.
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A provably good approximation algorithm for power optimization using multiple supply voltages
Hung-Yi Liu,Wan-Ping Lee,Yao-Wen Chang +2 more
- 04 Jun 2007
TL;DR: This paper addresses a voltage partitioning problem arising in MSV design during high-level synthesis and proposes an efficient alpha2-approximation algorithm for the problem, where a is the constant ratio of the maximum to the minimum voltages.
24
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