Journal Article10.1016/J.PARCO.2008.03.004
OpenFPGA CoreLib core library interoperability effort
Michael Wirthlin,D. Poznanovic,P. Sundararajan,A. Coppola,D. Pellerin,Walid Najjar,R. Bruce,M. Babst,O. Pritchard,Paolo Palazzari,Georgi Kuzmanov +10 more
- 01 May 2008
- Vol. 34, Iss: 4, pp 231-244
TL;DR: The paper reviews the current approach used by several high-level language compilers to integrate IP within their tool and proposes the CoreLib approach for standardizing this IP integration.
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Abstract: This paper begins by summarizing the goals of the OpenFPGA CoreLib Working Group to facilitate the interoperability of FPGA circuit cores within a variety of FPGA design tools, including high-level programming tools targeting FPGA architectures. This effort is contrasted with other IP reuse efforts. The paper reviews the current approach used by several high-level language compilers to integrate IP within their tool. The CoreLib approach for standardizing this IP integration is proposed followed by an example that demonstrates its utility. Finally, the current state of the effort and future plans are presented.
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Citations
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TL;DR: In this article, a data store stores for each of a plurality of nodes, each node comprising a wireless communication system element, a node image data comprising metadata about or otherwise associated with the node.
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