Report10.21236/ADA139912
On Mapping Homogeneous Graphs on a Linear Array-Processor Model.
I. V. Ramakrishnan,Donald S. Fussell,Abraham Silberschatz +2 more
- 01 Jan 1983
- pp 440-447
TL;DR: A complete characterization of the structure of a class of correctly mappable graphs is obtained and the formalism developed is used to synthesize algorithms for this model.
read more
Abstract: The authors present a formal model of linear array processors suitable for VLSI implementation as well as graph representation of programs suitable for execution on such a model. A distinction is made between correct mapping and correct execution of such graphs on this model. A complete characterization of the structure of a class of correctly mappable graphs is obtained. The formalism developed is used to synthesize algorithms for this model. 12 references.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
The Design of Optimal Systolic Arrays
Guo-Jie Li,Wah +1 more
TL;DR: In this paper, a methodology to systematically search and reduce this space and to obtain the optimal design is proposed, including matrix multiplication, finite impulse response filtering, deconvolution, and triangular matrix inversion.
252
Design of optimal systolic arrays
G.J. Li,Benjamin W. Wah +1 more
- 01 Jan 1985
TL;DR: In this paper, systolic arrays are characterized by three classes of parameters: the velocities of data flows, the spatial distributions of data, and the periods of computation, and a methodology to systematically search and reduce this space and to obtain the optimal design is proposed.
167
Array architectures for iterative algorithms
H.V. Jagadish,S.K. Rao,Thomas Kailath +2 more
- 01 Sep 1987
TL;DR: Regular mesh-connected arrays are shown to be isomorphic to a class of so-called regular iterative algorithms, which include arrays for Fourier Transform, Matrix Multiplication, and Sorting.
80
Selecting Systolic Designs Using Linear Transformations of Space -Time
Peter R. Cappello,Kenneth Steiglitz +1 more
- 28 Nov 1984
TL;DR: Linear transformations of space-time are used to explore design alternatives in a formal way and cellular computations for convolution and matrix product areused to illustrate this linear transformation technique.
21
References
Why systolic architectures
TL;DR: The basic principle of systolic architectures is reviewed and it is explained why they should result in cost-effective, highperformance special-purpose systems for a wide range of problems.
Systolic Arrays for (VLSI).
Hsiang-Tsung Kung,Charles E. Leiserson +1 more
- 01 Dec 1978
TL;DR: A systolic system is a network of processors which rhythmically compute and pass data through the system, and almost all processors used in the networks are identical, so that a regular flow of data is kept up in the network.
978
•Book Chapter
Let's Design Algorithms for VLSI Systems
H. T. Kung
- 01 Jan 1979
TL;DR: Examples of algorithms that are suitable for VLSI implementation are given, a taxonomy for algorithms based on their communication structures is provided, and some of the insights that are beginning to emerge from efforts in designing algorithms for V LSI systems are discussed.
296
•Proceedings Article
The rebound sorter: an efficient sort engine for large files
Tien Chi Chen,Vincent Y. Lum,Chin Tung +2 more
- 13 Sep 1978
TL;DR: A new sorting scheme, called the rebound sort, implementable on a variety of technologies, e.g., magnetic bubbles and charge-coupled devices is described, which accepts as input a sequence of records, sorts them, and outputs the sorted records automatically.
69