Proceedings Article10.1109/ETS.2006.35
On-Chip Test Generation Using Linear Subspaces
R. Das,Igor L. Markov,John P. Hayes +2 more
- 21 May 2006
- pp 111-116
TL;DR: This work proposes a novel solution that uses linear algebraic concepts to partition the vector space of tests into subspaces (clusters) and gives an algorithm to compute sets of basis vectors defining the clusters.
read more
Abstract: A central problem in built-in self test (BIST) is how to efficiently generate a small set of test vectors that detect all targeted faults. We propose a novel solution that uses linear algebraic concepts to partition the vector space of tests into subspaces (clusters). A subspace is defined by a compact set of basis vectors. We give an algorithm to compute sets of basis vectors defining the clusters. We also describe a low-cost logic circuit based on Gray codes that reproduces the subspaces from these basis vectors. Experimental results are presented which show that this approach reduces on-chip hardware overhead and test application time, while also guaranteeing full fault coverage.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
Adaptive online testing for efficient hard fault detection
Shantanu Gupta,Amin Ansari,Shuguang Feng,Scott Mahlke +3 more
- 04 Oct 2009
TL;DR: An adaptive online testing framework that is unique in its ability to assess the hardware health and apply suitably detailed tests and can achieve an 80% reduction in software test instructions over the lifetime of a 16-core CMP.
Retraction Note to: “Discrete Optimization Method Based on Grassmannian Parameterization in Multidimensional Dichotomic Data Structuring”
TL;DR: A vector parameterization of the Grassmannian Gr2(k, n) is proposed in this article, which makes it possible to minimize the amount of memory and reduce the number of operations required to solve the problem.
Discrete Optimization Method Based on Grassmannian Parameterization in Multidimensional Dichotomic Data Structuring
P. V. Gracheva
- 01 Jan 2011
TL;DR: A vector parameterization of the Grassmannian Gr2(k, n) is proposed, which makes it possible to minimize the amount of memory and reduce the number of operations required to solve the problem.
•Dissertation
Adaptive Architectures for Robust and Efficient Computing.
Shantanu Gupta
- 01 Jan 2011
TL;DR: Adaptive Architectures for Robust and Efficient Computing and compiler solutions that can effectively tackle reliabilit y, performance and energy-efficiency are proposed.
References
•Dissertation
On the generation of test patterns for combinational circuits
Sarita Thakar
- 01 Jan 1993
357
Bit-flipping BIST
Hans-Joachim Wunderlich,Gundolf Kiefer +1 more
- 10 Nov 1996
TL;DR: A scan-based BIST scheme is presented which guarantees complete fault coverage with very low hardware overhead, and it is shown that the output of an LFSR which feeds a scan path has to be modified only at a few bits in order to transform the random patterns into a complete test set.
Pattern generation for a deterministic BIST scheme
Sybille Hellebrand,Birgit Reeb,Steffen Tarnick,Hans-Joachim Wunderlich +3 more
- 01 Dec 1995
TL;DR: Experiments show that the area required for synthesizing a BIST scheme that encodes these patterns is significantly less than the area needed for storing a compact test set.
Test set embedding in a built-in self-test environment
S.B. Akers,W. Jansz +1 more
- 29 Aug 1989
TL;DR: The authors describe a built-in self-test (BIST) technique where the on-chip test pattern generator is a binary counter with associated XOR gates that forms the basis for the synthesis of the binary counter and accompanying (combinational) logic using linear algebraic techniques.
94
A BIST pattern generator design for near-perfect fault coverage
TL;DR: A new design methodology for a pattern generator is proposed, formulated in the context of on-chip BIST and can be used effectively to improve existing pattern generators for combinational logic and scan-based BIST structures.
45