Proceedings Article10.1109/CICC.1998.694914
On a pin versus gate relationship for heterogeneous systems: heterogeneous Rent's rule
Payman Zarkesh-Ha,Jeffrey A. Davis,W. Loh,James D. Meindl +3 more
- 11 May 1998
- pp 93-96
26
TL;DR: It is shown that, a composite Rent's rule successfully describes heterogeneous collection of megacells and the overall pin versus gate relationship of a heterogeneous system is derived based on the Rent'sRule parameters of each megACEll in the system.
read more
Abstract: In this paper the overall pin versus gate relationship of a heterogeneous system is derived based on the Rent's rule parameters of each megacell in the system. It is shown that, a composite Rent's rule successfully describes heterogeneous collection of megacells.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
System-level performance evaluation of three-dimensional integrated circuits
A. Rahman,Rafael Reif +1 more
- 01 Dec 2000
TL;DR: The wire (interconnect)-length distribution of 3-D integrated circuits (ICs) is derived using Rent's rule and following the methodology used to estimate two-dimensional (2-D) (wire-length distribution).
References
On a Pin Versus Block Relationship For Partitions of Logic Graphs
B.S. Landman,R.L. Russo +1 more
TL;DR: Partitions of the set of blocks of a computer logic graph, also called a block graph, into subsets called modules demonstrate that a two-region relationship exists between P, the average number of pins per module, and B, theaverage number of blocks per module.
755
A system-level circuit model for multi- and single-chip CPUs
H. Bakoglu,J. Meindl +1 more
- 01 Jan 1987
TL;DR: A system level circuit model has been used to predict the performance of microprocessors, gate arrays, and mainframe computers implemented in several IC technologies and predictions indicate that in ten years a 0.7μm CMOS micro-processor will execute 30-60 MIPS.
39
A priori wiring estimations and optimal multilevel wiring networks for portable ULSI systems
Jeffrey A. Davis,V.K. De,James D. Meindl +2 more
- 28 May 1996
TL;DR: A rigorous derivation of a complete wire length distribution for on-chip random logic networks is performed and then used to describe an optimal architecture for a multilevel wiring network that provides maximum interconnect density and minimum power for a portable ULSI system.
22
Placement and average interconnection lengths of computer logic
TL;DR: In this article, an upper bound on expected average interconnection length, based on partitioning results, is given for linear and square arrays of gates, which gives significantly lower interconnection lengths than the bound based upon random placement.