Object-Oriented Embedded System Development Based on Synthesis and Reuse of OO-ASIPs

TL;DR: This work adopts the object-oriented methodology for the system-level model and implements methods of the class library as the instruction-set of the processor, which allows the processor to be synthesised just once, but, by programming, to be reused several times and specialised to new applications that use the same class library.

Abstract: We present an embedded-system design flow, discuss its details, and demon- strate its advantages. We adopt the object-oriented methodology for the system-level model because software dominates hardware in embedded systems and the object- oriented methodology is already established for software design and reuse. As the building-block of system implementation, we synthesise application-specific processors that are reusable, through programming, for several related applications. This addresses the high cost and risk of manufacturing specialised hardware tailored to only a single application. Both the processor and its software are generated from the model of the system by the synthesis and compilation procedures provided. We observe that the key point in object-oriented methodology is the class library, and hence, we implement methods of the class library as the instruction-set of the processor. This allows the processor to be synthesised just once, but, by programming, to be reused several times and specialised to new applications that use the same class library. An important point here is that the processor allows its instructions to be selectively overridden by soft- ware routines; this not only allows augmentation of processor capabilities in software, but also enables a structured approach to make software patches to faulty or outdated hardware. A case study illustrates application of the methodology to various applica- tions modelled on top of a common basis class library, and moreover, demonstrates new application-specific opportunities in power management (and area-management for FPGA implementations) resulting from the structure of the processor based on deactivation of unused features.