Patent
Nonvolatile memory system and associated programming methods
Jin-hyeok Choi
- 30 Mar 2007
54
TL;DR: In this paper, a nonvolatile memory system includes a host system, a memory controller, and a flash memory chip including multi-level flash memory cells, and the memory controller includes a backup memory adapted to store a backup copy of previously programmed data.
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Abstract: A nonvolatile memory system includes a host system, a memory controller, and a flash memory chip including multi-level flash memory cells. The memory controller includes a backup memory adapted to store a backup copy of previously programmed data from the multi-level flash memory cells when further programming of the multi-level flash memory cells fails. The backup copy of the previously programmed data is used to detect and correct any errors in the previously programmed data before reprogramming the previously programmed data to different multi-level memory cells in the nonvolatile memory system.
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Citations
Patent
Memory system and method of accessing a semiconductor memory device
Jaesoo Lee,Kangho Roh,Wonhee Cho,Hojun Shim,Young-joon Choi,Jae-hoon Heo,Je-Hyuck Song,Seung-Duk Cho,Seon-Taek Kim,Moon-Wook Oh,Jong Tae Park,Won-Moon Cheon,Chanik Park,Yang-Sup Lee +13 more
- 15 Aug 2011
TL;DR: In this article, a memory system is provided with a processor, a main memory, and a flash memory, which includes a non-volatile memory device and a controller configured to drive a control program to control the nonvolatile device.
191
Patent
Memory system and operating method thereof
Jaehong Kim,Kijun Lee,Yongjune Kim,Heeseok Eun +3 more
- 28 Sep 2016
TL;DR: In this article, the operating method of an observation memory cell at least one time with different read voltages to configure a first read data symbol, reads a plurality of interference memory cells adjacent to the observation memory cells at least once, with different voltages, to configure second read data symbols, and determines a logical value of the observed memory cell based on the first data symbol and the second read symbol.
89
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Method and apparatus for optimizing the performance of a storage system
Holloway H. Frost,Daniel E. Scheel +1 more
- 16 Jun 2014
TL;DR: In this paper, the storage controller receives a WRITE request from an external host containing data and an address, forwards the received WRITE request to the FLASH storage system and associates the address provided in the WRITE request with a selected alternative address.
86
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Error recovery for flash memory
Yingquan Wu,Marcus Marrow +1 more
- 02 Dec 2014
TL;DR: In this article, a page type which failed error correction decoding is received and a threshold to adjust is selected from a plurality of thresholds based at least in part on the page type.
75
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Nonvolatile memory device having flag cells for storing MSB program state
Dong-Kyu Youn,Jin-Yub Lee +1 more
- 27 Dec 2006
TL;DR: In this paper, a nonvolatile memory device comprises a memory cell array comprising memory cells arranged in rows and first columns and flag cells arranged on the rows and second columns, and a page buffer configured to read flag data bits from flag cells in a selected row via the second columns.
27
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Sergey Anatolievich Gorobets,Reuven Elhamias,Carlos J. Gonzalez,Kevin M. Conley +3 more
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TL;DR: In this article, the authors propose to defer execution of some of the corrective action when the memory system has other high priority operations to perform, in order to balance the sometimes conflicting needs to maintain data integrity and system performance.
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TL;DR: In this article, the authors propose to use a non-volatile memory system without incurring additional data transfer latency by transferring data from a controller to a second memory chip and a programming operation is caused to begin in that chip.
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Method and apparatus for performing error correction on data read from a multistate memory
Frankie F. Roohparvar
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TL;DR: In this paper, a method and apparatus for performing error correction on data read from a multistate memory is described, where each cell in a memory device is read to generate a read voltage determined by a state of the cell and one of an ordered succession of encoded signals is selected based on the read voltage.
187
Patent
Data management for multi-bit-per-cell memories
Sau Ching Wong,Hock Chuen So +1 more
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TL;DR: A multi-bit-per-cell memory can reduce the effect of defects and data errors by scrambling data bits before writing data as mentioned in this paper, which prevents storage of consecutive bits in the same memory cell.
186
Patent
Memory controller for multilevel cell memory
Fujitsu Limited Keisuke Kawasaki-shi Kanagawa Kanazawa,Hiroaki Watanabe,Fujitsu Limited Yoshinobu Kawasaki-shi Kanagawa Higuchi,Fujitsu Limited Hideki Kawasaki-shi Kanagawa Arakawa,Okumura Yoshiki,Sekino Yutaka +5 more
- 18 Mar 2002
TL;DR: In this paper, a N-level cell memory controlled by the memory controller of the invention has an internal configuration in which the plurality of data input/output terminals connected to the second data bus are separated into first through Mth data input and output terminal groups, such that there is no redundancy in the n bits of data associated with one Nlevel cell.
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