Patent
Network data flow optimization
Todd Rimmer
- 28 Jun 2002
83
TL;DR: In this paper, a shared I/O subsystem having a plurality of ports, where each of the ports includes an address bit and first and second masks associated therewith, is considered.
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Abstract: A shared I/O subsystem having a plurality of ports, where each of the ports includes a plurality of address bits and first and second masks associated therewith The shared I/O subsystem receives a data packet from a first of the plurality of ports, selects from one or more tables the plurality of address bits and the first and second masks associated with the first port, applies an AND function to the address bits and the first mask associated with the first port, applies an OR function to the result of applying the AND function and the second mask associated with the first port, and selectively transmits the data packet to one or more of the ports in accordance with a result of applying the OR function
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Citations
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References
Patent
Packet switched cache coherent multiprocessor system
Nishtala Satyanarayana,Ebrahim Zahir,William C. Van Loo,Kevin Normoyle,Kohn Leslie,Louis F. Coffin +5 more
- 31 Mar 1995
TL;DR: In this article, a multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller, and the system controller maintains a set of duplicate cache tags (Dtags) for each data processor.
88