Proceedings Article10.1145/223982.224451
Multiscalar processors
Gurindar S. Sohi,Scott E. Breach,T. N. Vijaykumar +2 more
- 01 May 1995
pp 414-425
927
TL;DR: The philosophy of the multiscalar paradigm, the structure ofMultiscalar programs, and the hardware architecture of a multiscalars processor are presented.
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Abstract: Multiscalar processors use a new, aggressive implementation paradigm for extracting large quantities of instruction level parallelism from ordinary high level language programs. A single program is divided into a collection of tasks by a combination of software and hardware. The tasks are distributed to a number of parallel processing units which reside within a processor complex. Each of these units fetches and executes instructions belonging to its assigned task. The appearance of a single logical register file is maintained with a copy in each parallel processing unit. Register results are dynamically routed among the many parallel processing units with the help of compiler-generated masks. Memory accesses may occur speculatively without knowledge of preceding loads or stores. Addresses are disambiguated dynamically, many in parallel, and processing waits only for true data dependences.This paper presents the philosophy of the multiscalar paradigm, the structure of multiscalar programs, and the hardware architecture of a multiscalar processor. The paper also discusses performance issues in the multiscalar model, and compares the multiscalar paradigm with other paradigms. Experimental results evaluating the performance of a sample of multiscalar organizations are also presented.
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Citations
Amdahl's Law in the Multicore Era
Mark D. Hill,Michael R. Marty +1 more
TL;DR: Augmenting Amdahl's law with a corollary for multicore hardware makes it relevant to future generations of chips with multiple processor cores.
Complexity-effective superscalar processors
Subbarao Palacharla,Norman P. Jouppi,James E. Smith +2 more
- 01 May 1997
TL;DR: A microarchitecture that simplifies wakeup and selection logic is proposed and discussed, which will help minimize performance degradation due to slow bypasses in future wide-issue machines.
Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor
Dean M. Tullsen,Susan J. Eggers,Joel Emer,Henry M. Levy,Jack L. Lo,Rebecca L. Stamm +5 more
- 01 May 1996
TL;DR: This paper presents an architecture for simultaneous multithreading that minimizes the architectural impact on the conventional superscalar design, has minimal performance impact on a single thread executing alone, and achieves significant throughput gains when running multiple threads.
LogTM: log-based transactional memory
Kevin E. Moore,Jayaram Bobba,M.J. Moravan,Mark D. Hill,Darien Wood +4 more
- 27 Feb 2006
TL;DR: This paper presents a new implementation of transactional memory, log-based transactionalMemory (LogTM), that makes commits fast by storing old values to a per-thread log in cacheable virtual memory and storing new values in place.
Baring it all to software: Raw machines
E. Waingold,Michael Taylor,Devabhaktuni Srikrishna,Vivek Sarkar,Whay S. Lee,Victor W. Lee,Jason Kim,Matthew I. Frank,P. Finch,Rajeev Barua,Jonathan Babb,Saman Amarasinghe,Anant Agarwal +12 more
TL;DR: The most radical of the architectures that appear in this issue are Raw processors-highly parallel architectures with hundreds of very simple processors coupled to a small portion of the on-chip memory, allowing synthesis of complex operations directly in configured hardware.
725
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The expandable split window paradigm for exploiting fine-grain parallelism
Manoj Franklin,Gurindar S. Sohi +1 more
- 01 Mar 1995
TL;DR: A new processing paradigm, called the Expandable Split Window (ESW) paradigm, for exploiting fine-grain parallelism, which considers a window of instructions as a single unit, and exploits fine- grain parallelism by overlapping the execution of multiple windows.
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