Patent
Multiprocessor computer system
Asbjoern Smitt
- 16 Sep 1982
86
TL;DR: In this paper, the memory bus means are configurated to allow direct data transfer between any memory fraction of central processing unit systems without interfering with the central processing units that being controlled by direct memory access control means.
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Abstract: A multiprocessor computer system wherein memory bus means of separate central processing unit systems are interfaced to an intermemory communication network for transfer of data between memories of said separate central processing unit systems. The intermemory communciation network comprises a plurality of preferably passive intermemory communication links being tapped for connection to link adapters interfacing a number of central processing unit systems to each intermemory communication link. The number of central processing unit system may be different for different intermemory communciation links. The memory bus means are configurated to allow for direct data transfer between any memory fraction of central processing unit systems without interfering with the central processing units that being controlled by direct memory access control means. The multiprocessor computer system includes separate configuration control means being effective to reconfigurate the overall system in the event of failure. The reconfiguration comprises switching of fractions of memory between the memory bus means of at least two central processing unit sytems. Some of said memory fractions being directly addressable by a respective peripheral processor, at least one of said peripheral processors backing up the others for obtaining N+1 redundancy.
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Citations
Patent
User scheduled direct memory access using virtual addresses
Russ W. Herrell,Thomas P Morrissey +1 more
- 11 Mar 1991
TL;DR: In this paper, an intelligent direct memory access (DMA) controller interprets user commands from a host system, translates virtual addresses from the user applications program to physical addresses, and retrieves blocks of data from the main system memory at the request of the user's code, rather than at the permission of the kernel code of the host system.
204
Patent
Interprocessor switching network
Read Edgar Lawrence,Grant Elwyn Everett,Keto Gary Alan,Sharlene Chieh-Hsia Lin,Morgan James Douglas,Robert E. Nimon,Oliver Gene Oldham,Allen Ray Adams,Salmones Jose Aurelio +8 more
- 10 Jan 1992
TL;DR: In this paper, a digital switching network for providing simultaneous connections among user processors of processor-based communications equipment is presented, where the user processors act as originators and destinations of data communications packets.
179
Patent
Self configuring computer network with automatic bus exchange of module identification numbers and processor assigned module numbers
Claude R. Ceccon,Joseph N. Kovara,Paul C. Mioduski +2 more
- 06 Dec 1983
TL;DR: In this article, the closest interface card of each local bus responds by transmitting information from its identification ROM to the requesting local processor, which then assigns an address to the closest interfaces card, and then automatically sets circuitry that enables the next closest interfaces to respond to the initial address.
121
Patent
Digital computer with cache capable of concurrently handling multiple accesses from parallel processors
Blau Jonathan Seth,Robert L. Fredieu,Michael L. Ziegler +2 more
- 17 Jun 1986
TL;DR: A cache memory capable of concurrently accepting and working on completion of more than one cache access from a plurality of processors connected in parallel is discussed in this paper. But the work in this paper is restricted to the case of a single processor.
120
Patent
Direct memory access apparatus and methods for transferring data between buses having different performance characteristics
William M. Johnson,Timothy Alan Olson,Doruu Jiyon Daton,Sherman Lee,David W. Stoenner +4 more
- 15 Dec 1987
TL;DR: In this paper, direct memory access (DMA) is used to transfer data between a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus").
103
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Patent
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Patent
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Christian Jakob Jenny,Karl Albert Dr Ing Kuemmerle +1 more
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Patent
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Domenic R. Romano,Hans H. Henneberg,James W. Pratt,Maurice A. Coppelman +3 more
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