Multiplication of Multidigit Numbers on Automata

TL;DR: This paper explores the effects of truncation schemes in recursive multiplier architectures in terms of the trade-off between circuit complexity versus introduced truncation errors, and presents an in depth analysis of the error associated with truncation scheme directly targeting recursive multipliers that minimize the truncation error by carefully choosing data-dependent correction terms.

TL;DR: In this paper, the authors present new speed records for multi-precision multiplication on the AVR ATmega family of 8-bit microcontrollers, achieving a speedup of more than 15% for the multiplication of two 160-bit integers.

TL;DR: Hardware design of multidigit integer multiplication based on Karatsuba algorithm is described and its VLSI realization is evaluated in terms of the cost, performance, and energy consumption to help system designers for applications requiring multidIGit multiplication to select design alternatives including ASIC realization.

TL;DR: This work presents an efficient implementation of a programmable Finite Impulse Response (FIR) filter based on the use of the Karatsuba Multiplication Algorithm (KMA), which is a fast divide and conquer algorithm for the multiplication of large numbers.