Multiple-level memory cells and error detection

TL;DR: In this paper, a method for reading a representation of a codeword stored in a multi-level-cell (MLC) memory by comparing cell threshold voltages in the MLC memory to hard bit thresholds to generate hard bit values and to soft bit threshold to generate soft bit values is presented.

TL;DR: In this paper, the mapping of received digit patterns to shaping digit patterns obeys a shaping constraint that limits, to an uppermost amount, an amount of consecutive digits of the shaping digit pattern allowed to have a particular digit value.

TL;DR: In this paper, a method, system and memory controller for implementing ECC (Error Correction Codes) control to provide enhanced endurance and data retention of flash memories is provided, which includes a threshold voltage monitor to determine VT degradation of cells and blocks; the VT monitor configured to store information about the determined VT degradation.

TL;DR: In this paper, the authors proposed a method for correcting at least one error in readings of electricity meters, the method including receiving first readings of regular meters measuring electric energy delivered in each of a group of cables fed from a same distribution node in an electric grid during a period of time, and receiving second readings of check meters measuring electricity delivered by each of combinations of cables in the group.

TL;DR: In this article, an analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of levels, where the output of the analog to digital converter has an input and an output.

TL;DR: In this article, the group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from multiple possible data values, each possible data value corresponds to one range of multiple non-overlapping ranges of analog voltages.

TL;DR: This work has developed a 144 Mb 8-level NAND flash memory with 0.5 MB/s programming throughput which is 1.7 times faster than the conventional simultaneous programming scheme used in NANDflash memory.

TL;DR: In this paper, a method of storing, sensing and restoring 1.5 bits per cell of a plurality of memory cells in dynamic random access memory is comprised of storing one of the three voltage levels( 0, Vcc/ 2, VCC) into memory cell with a word line voltage (Vccp) in the write stage, applying Vcc 2 to bit line and Vccp to word line in the read/refresh stage, a bit line voltage changing detection circuit (an asymmetrical sense amplifier, ASA, which is connected to a multiplex), a multiple