Patent
Multiple-core computer processor for reverse time migration
John Shalf,David Donofrio,Leonid Oliker,Jens Krueger,Samuel Williams +4 more
- 26 Oct 2012
31
TL;DR: In this paper, a multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, each of the plurality of caches being associated with one and only one of the processor cores, and each memory associated with a different set of at least one processor cores and each of memories being configured to be visible in a global memory address space such that the plurality memories are visible to two or more of the processors.
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Abstract: A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores, wherein at least one of a number of the processor cores, a size of each of the plurality of caches, or a size of each of the plurality of memories is configured for performing a reverse-time-migration (RTM) computation.
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Citations
Patent
Utilization of a distributed index to provide object memory fabric coherency
Steven J. Frank,Larry Reback +1 more
- 20 Jan 2016
TL;DR: In this paper, a hierarchy of object routers may communicatively couple the object memory modules and maintain an object cache state for the memory objects and/or portions contained in the memory modules below the object router in the hierarchy.
28
Patent
Work unit stack data structures in multiple core processor system for stream data processing
Charles Edward Gray,Bertrand Serlet,Felix A. Marti,Wael Noureddine,Pratapa Reddy Vaka +4 more
- 20 Nov 2018
TL;DR: Work unit stack data structures as mentioned in this paper are used in a run-to-completion programming model of an operating system executed by a multiple-core processor system for processing streams of data at high rates.
20
Patent
Data processing unit for stream processing
Pradeep Sindhu,Jean-Marc Frailong,Wael Noureddine,Felix A. Marti,Deepak Goel,Goyal Rajan,Bertrand Serlet +6 more
- 10 Jul 2018
TL;DR: In this article, a data processing unit (DPU) is designed for a data-centric computing model in which the data processing tasks are centered around the DPU, which is viewed as a highly programmable, high-performance I/O and data-processing hub designed to aggregate and process network and storage IO to and from other devices.
19
Patent
Infinite memory fabric hardware implementation with router
Steven J. Frank,Larry Reback +1 more
- 01 Jun 2016
TL;DR: In this paper, a hardware-based processing node of an object memory fabric is described, where each memory object is created natively within the memory module and accessed using a single memory reference instruction without Input/Output (I/O) instructions.
19
Patent
Infinite memory fabric streams and APIs
Steven J. Frank,Larry Reback +1 more
- 31 May 2016
TL;DR: In this paper, object memory fabric streams and application programming interfaces (APIs) correspond to a method to implement a distributed object memory and to support hardware, software, and mixed implementations.
15
References
Patent
Multi-petascale highly efficient parallel supercomputer
Sameh W. Asaad,Ralph Bellofatto,Michael A. Blocksome,Matthias A. Blumrich,Peter Boyle,Jose R. Brunheroto,Dong Chen,Chen-Yong Cher,George Liang-Tai Chiu,N. H. Christ,Paul W. Coteus,Kristan D. Davis,Gabor Dozsa,Alexandre E. Eichenberger,Noel A. Eisley,Matthew R. Ellavsky,Kahn C. Evans,Bruce M. Fleischer,Thomas W. Fox,Alan Gara,Mark E. Giampapa,Thomas M. Gooding,Michael K. Gschwind,John A. Gunnels,Shawn A. Hall,Rudolf A. Haring,Philip Heidelberger,Todd A. Inglett,Brant L. Knudson,Gerard V. Kopcsay,Sameer Kumar,Amith R. Mamidala,James Anthony Marcella,Mark G. Megerian,Douglas R. Miller,Samuel J. Miller,Adam J. Muff,Michael B. Mundy,John Kevin Patrick O'Brien,Kathryn M. O'Brien,Martin Ohmacht,Jeffrey J. Parker,Ruth J. Poole,Joseph D. Ratterman,Valentina Salapura,David L. Satterfield,Robert M. Senger,Brian E. Smith,Burkhard Steinmacher-Burow,William Maupin Stockdell,Craig B. Stunkel,Krishnan Sugavanam,Yutaka Sugawara,Todd E. Takken,Barry M. Trager,James L. Van Oosten,Charles D. Wait,Robert E. Walkup,Alfred T. Watson,Robert W. Wisniewski,Peng Wu +60 more
- 10 Jan 2011
TL;DR: A multi-petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, allows for a maximum packaging density of processing nodes from an interconnect point of view.
391
Patent
Processing architecture having a compare capability
Ashley Saulsbury
- 08 Mar 2001
TL;DR: In this paper, a register file, comparison logic, decode logic, and a store path are disclosed for a compare instruction. But decoding the register file is not a straightforward task, as it is computationally computationally expensive.
140
Patent
Pseudo-analytical method for the solution of wave equations
John Etgen,Sverre Brandsberg-Dahl +1 more
- 06 Oct 2009
TL;DR: The instant method as mentioned in this paper is a method for numerically propagating waves or solving wave equations on a digital computer, which can be used to compute highly accurate solutions to the wave equation, in fact in some cases it computes the analytical solution, something previously considered impossible.
70
Energy-Efficient Computing for Extreme-Scale Science
David Donofrio,L. Oliker,John Shalf,Michael Wehner,C. Rowen,J. Krueger,Shoaib Kamil,Marghoob Mohiyuddin +7 more
TL;DR: A many-core processor design for high-performance systems draws from embedded computing's low-power architectures and design processes, providing a radical alternative to cluster solutions.
61
Hardware/software co-design for energy-efficient seismic modeling
Jens Krueger,David Donofrio,John Shalf,Marghoob Mohiyuddin,Samuel Williams,Leonid Oliker,Franz-Josef Pfreundt +6 more
- 12 Nov 2011
TL;DR: This work has developed an FPGA-accelerated architectural simulation platform to accurately model the power and performance of the Green Wave design, a general-purpose manycore chip design optimized for high-order wave equations called "Green Wave".