Multiple-bit error correction in computer main memory

TL;DR: In this paper, an EDC with 128-bits of data and a check bit field 41-bits wide, using a BCH code, constructed in ASIC sea-of-gates technology using about 87,000 logic gates, can correct 5-bits in error and can detect 6-bits.

Abstract: A computer system includes a main memory that is able to make use of DRAM memory devices having a relatively high level of bad cells (hard faults). An EDC circuit is provided which uses combinatorial logic to perform a BCH code type of error detection and correction. A primary feature is the recognition that due to use of high density integrated circuits - gate arrays - it is no longer necessary to use sequential logic to decode the multiple-bit error correcting codes. An EDC with 128-bits of data and a check bit field 41-bits wide, using a BCH code, constructed in ASIC sea-of-gates technology using about 87,000 logic gates, can correct 5-bits in error and can detect 6-bits in error. By using multiple-bit EDC in the controller for main memory, it is no longer necessary that all DRAM devices be ostensibly "perfect." A certain density of non-functional memory cells can be tolerated, yet the memory system will still return perfect data. The added cost of multiple-bit EDC, including the added cost of extra storage for the check bits and the EDC circuit itself, is more than compensated by reduced cost of the DRAMs. In a addition the computer system includes a solid-state disk type memory for a computer system is able to make use of DRAM memory devices having a relatively high level of bad cells (hard faults). An EDC circuit is employed to perform a Reed-Solomon code type of error detection and correction. A primary feature is the recognition that it is no longer necessary that all DRAM devices be ostensibly "perfect." A certain density of non-functional memory cells can be tolerated, yet the memory system will still return perfect data. The added cost of multiple-bit EDC, including the added cost of extra storage for the check bits and the EDC circuit itself, is more than compensated by reduced cost of the DRAMs. A preferred data formatter circuit to convert between symbol and word data is also described.