Patent
Multicomputer digital processing system
M. Nicholas Matelan,Thomas G. Leete,Leslie Zsohar,Michael Kent Blanchard,Abdolreza Naeini,Jacob Hsu,Dennis Kyle Smith +6 more
- 30 Oct 1985
99
TL;DR: In this paper, a multiple computer digital processing system including several Local Buses positioned orthogonally to a Common Bus is described, where each Local Bus is connected to the Common Bus through a plugable connected Common Bus interface card to provide a transfer of information between Local BUs across the Common bus.
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Abstract: A multiple computer digital processing system including several Local Buses positioned orthogonally to a Common Bus. Each Local Bus is connected to the Common Bus through a plugably connected Common Bus interface card to provide a transfer of information between Local Buses across the Common Bus. Computer cards, memory cards and other device cards may be plugably connected to the Local Bus to communicate with each other via the Local Buses and Common Bus. The number and types of cards connected and even the number of Local Buses connected to the Common Bus may be varied according to the requirements of each application. Additionally, the Common Bus includes a shared memory accessible by all devices and an InterComputer Interrupt circuit providing interrupts to the computer cards. Further the computer cards are plugably connectable to a Peripheral Bus to provide communications with peripheral devices located externally to the system. All cards connected to the Local Buses and Common Bus include monitor circuits connected through a Test Bus to a System Monitor that configures the system according to the cards connected and the application requirements, detects errors, monitors performance, and provides fault tolerant repair capability under operator supervision.
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Citations
Patent
High reliability memory module with a fault tolerant address and command bus
Kevin C. Gower,Bruce G. Hazelzet,Mark W. Kellogg,David J. Perlman +3 more
- 20 Apr 2006
TL;DR: In this article, a high reliability dual-inline memory module with a fault tolerant address and command bus for use in a server is presented. But the memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a DRAM, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and
220
Patent
Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters
Thomas W. Craft,Bradley T. Herrin,Thomas E. Ludwig +2 more
- 30 Jun 1992
TL;DR: In this article, an arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master, which is responsive to high priority bus activities such as memory refresh cycles and DMA cycles to temporarily transfer control of the shared bus from the bus master to a circuit controlling the high priority activity.
200
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System having independently addressable bus interfaces coupled to serially connected multi-ported signal distributors generating and maintaining frame based polling schedule favoring isochronous peripherals
Shaun Knoll,Charles Jeff Morriss,Shelagh Callahan,Ajay V. Bhatt,Kottal Puthiya Nizar,Richard M. Haslam,Andrew M. Volk,Sudarshan Bala Cadambi +7 more
- 31 Oct 1994
TL;DR: In this paper, a hierarchical serial bus assembly for serially interfacing a number of isochronous and asynchronous peripherals to the system unit of a computer system is described.
167
Patent
System for computer peripheral bus for allowing hot extraction on insertion without disrupting adjacent devices
Bartol Thomas Matthew
- 07 Oct 1992
TL;DR: In this paper, a method and apparatus for rapid interconnection (hot plugging) peripheral device interface circuits to a computer bus is disclosed. The interconnections are completed using three sets of conductors in the sequence: common grounds, power from the bus and data lines.
162
Patent
Method and apparatus for automatic initialization of pluggable option cards
Chester Asbury Heath,John K. Langgood,Ronald Eugene Valli +2 more
- 04 Jan 1991
TL;DR: In this article, a data processing system includes a planar board having a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets or slots, each adapted to receive a selected one of a plurality of different and/or similar option cards.
128
References
Patent
Modular computer system
Jack J. Stiffler,Richard Alan Karp,James M. Nolan,Michael J. Budwey,David Alexander Wallace +4 more
- 30 Aug 1983
TL;DR: In this paper, a multi-processor computer system is disclosed in which processing elements, memory elements and peripheral units can be physically added and removed from the system without disrupting its operation or necessitating any reprogramming of software running on the system.
216
Patent
Data processing systems and methods
Philip Malcolm Neches
- 19 Apr 1984
TL;DR: In this paper, a multiprocessor system intercouples the processors with an active logic network having a plurality of priority determining nodes, where messages applied concurrently to the network in groups are sorted, using the data content of the messages, to a single or common priority message which is distributed to all the processors.
146
Patent
Selection of addressed processor in a multi-processor network
John O. Besemer,Clifford J. Bellamy +1 more
- 21 Dec 1978
TL;DR: In this article, a hierarchy of processors with a plurality of addressable memory storage units is described, where a "Sender" processor can address a "Receiver" processor within a system of processors and select the first processor which is found to be in idle condition, and whereby a Sender can address processors of a specially indicated type.
143
Patent
Multiprocessor computer system
Asbjoern Smitt
- 16 Sep 1982
TL;DR: In this paper, the memory bus means are configurated to allow direct data transfer between any memory fraction of central processing unit systems without interfering with the central processing units that being controlled by direct memory access control means.
86
Pluribus—An operational fault-tolerant multiprocessor
D. Katsuki,E.S. Elsam,W.F. Mann,Eric Roberts,John G. Robinson,F.S. Skowronski,E.W. Wolf +6 more
- 01 Oct 1978
TL;DR: The authors describe the Pluribus multiprocessor system, outline several techniques used to achieve fault-tolerance, describe their field experience to date, and mention some potential applications that might benefit from this approach.
85
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