Patent
Multi-processor data processing system
Yoshiaki Tokita,Keisuke Okajima +1 more
- 20 Jun 1978
85
TL;DR: In this paper, a queue buffer accompanied by an intercommunicating information read/write control unit is used to control the transmission and reception of information between the processors and the queue buffer.
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Abstract: A multi-processor data processing system comprises, in addition to a main memory unit which is common to a plurality of processors, a queue buffer which is common to the processors to store intercommunicating information for the processors, whereby when each processor completes a process, information relating to the process is stored in the main memory unit and the first address of this information or the intercommunicating information is transmitted to the queue buffer from which any idle or vacant processor reads out the intercommunicating information. The queue buffer accompanies an intercommunicating information read/write control unit which controls the transmission and reception of intercommunicating information between the processors and the queue buffer. In this way, intercommunicating processing is accomplished without requiring any access to the main memory unit and without requiring the operation of an operating system for intercommunication. Thus, the multi-processor data processing system has a reduced burden on the main memory unit and the operating system and is efficient and economical.
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Citations
Patent
Modular computer system
Jack J. Stiffler,Richard Alan Karp,James M. Nolan,Michael J. Budwey,David Alexander Wallace +4 more
- 30 Aug 1983
TL;DR: In this paper, a multi-processor computer system is disclosed in which processing elements, memory elements and peripheral units can be physically added and removed from the system without disrupting its operation or necessitating any reprogramming of software running on the system.
216
Patent
Multiple-microcomputer processing
Charles F. Summer,Robert O. Pettus,Ronald D. Bonnell,Michael N. Huhns,Larry M. Stephens +4 more
- 19 Nov 1980
TL;DR: The architecture of a special-purpose multiprocessor, hierarchically structured and functionally distributed, having ditributed cache memory for local processing and a common applictions task manager in each microcomputer is described in this article.
215
Patent
Interface between a pair of processors, such as host and peripheral-controlling processors in data processing systems
Barry L. Rubinson,Edward A. Gardner,William A. Grace,Richard F. Lary,Dale R. Keck +4 more
- 04 Oct 1982
TL;DR: In this paper, the authors present an interface mechanism between two processors, such as a host processor (70) and a processor (31) in an intelligent controller for mass storage devices (40), and utilizing a set of data structures employing a dedicated communications region (80A) in host memory.
186
Patent
Interface for use between a memory and components of a module switching apparatus
David L. Budde,David G. Carson,David B. Johnson,Doran Wilde +3 more
- 04 Jan 1982
TL;DR: In this paper, the memory bus is a packet-oriented bus, which is composed of processor buses (105) and corresponding control lines; and memory buses (107) with corresponding control line (108).
142
Patent
High speed parallel bus and data transfer method
Raymond S. Tetrick,John Beaston,Robert L. Farrell,Alireza Sarabi,Sudarshan Balachandran,Edwin L. Jacks,Steven D. Kassel +6 more
- 25 Nov 1983
TL;DR: In this article, a multiple bus system architecture and improved data transfer methods are disclosed for transferring data between a plurality of data processing resources, which includes both a parallel and serial bus which interconnects data processing units and peripheral devices (collectively referred to as "agents") to permit the exchange of data and messages at high speed using a minimum of handshake events before the actual data transfer.
141
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Patent
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Richard A. Garlic
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TL;DR: In this paper, the use of general purpose, non-dedicated registers is considered to avoid the need for multi-phase clocking, and a single phase clock is defined for all portions of a micro-instruction.
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TL;DR: In this article, an information processing system comprising a central processing unit, an input/output unit, and a first-in-first-out stack connected between these units is provided.
53
Patent
Method and apparatus for controlling a multiprocessor system
Jr. Geoffrey Probert
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TL;DR: In this article, a multiprocessor system having a computer poller and a memory poller for controlling information transfer over a time multiplex bus between a plurality of computers and an interleaved memory comprising of sections is presented.
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Patent
Multistage sorter having pushdown stacks with concurrent access to interstage buffer memories for arranging an input list into numerical order
Michel A. Rohner
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TL;DR: In this paper, an input list of N numbers is clocked through a first sort stage having S1 locations entered into an interstage memory as S2 groups of S1 numbers each.
26