Molecular field programmable gate array

Patent

Molecular field programmable gate array

- 01 Sep 1999

55

TL;DR: In this article, an architectural concept for field programmable gate array circuits is presented based on a universal fabric of cells called look-up tables arranged in a direct, repeatable spatial grid.

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References

Patent

Programmable logic cell and array

Frederick C. Furtek

- 28 Aug 1992

TL;DR: An improved programmable logic cell (1) as discussed by the authors is a two-dimensional array of direct connections between a cell and its four nearest neighbors, one to its left (or to the West) (3a, 3b, 7a, 7b, 8a, 8b) and another to its right (or, to the East) (5a, 5b, 9a, 9b, 10b, 11a, 12b), one above (or below) (2a, 2b, 6a, 6b), and one below (

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392

Patent

Programmable analog array circuit

Edmund Pierzchala, +1 more

- 22 Dec 1994

TL;DR: In this article, a programmable analog or mixed analog/digital circuit is described, whose input and output signals are analog or multi-valued in nature, and primarily continuous in time.

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154

Patent

Bus structure for modularized chip with FPGA modules

David J. Ridgeway

- 14 Oct 1997

TL;DR: An on-chip bus structure for use in a modularized integrated circuit chip including an FPGA module(s) was proposed in this paper. But this bus and module structure is limited to a single chip.

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140

Proceedings Article•10.1109/FPGA.1998.707883

Plastic cell architecture: towards reconfigurable computing for general-purpose

K. Nagami, +4 more

- 15 Apr 1998

TL;DR: Plastic Cell Architecture is a reference for implementing a mechanism of a fully autonomous reconfigurability, which is a further step toward general-purpose reconfigurable computing, introducing variable- and programmable-grain parallelism to wired logic computing.

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104

Patent

Field programmable gate array having access to orthogonal and diagonal adjacent neighboring cells

Frederick C. Furtek, +2 more

- 24 Sep 1997

TL;DR: In this article, a field programmable gate array (FPGA) comprising a matrix of programmable logic cells, a bus network of local and express bus lines, and a system of perimeter I/O pads is disclosed.

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