Journal Article10.1049/EL:19890636
Modified CORDIC algorithm with reduced iterations
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TL;DR: A modified CORDIC algorithm is presented that offers a considerable latency time reduction and chip area savings when compared with the original CORDic method.
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Abstract: In this contribution we present a modified CORDIC algorithm that offers a considerable latency time reduction and chip area savings when compared with the original CORDIC method. The operations used are adds, shifts, and multiplication or division.
read more
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Citations
Low latency time CORDIC algorithms
TL;DR: An improved method which guarantees a constant scale factor when employing redundant addition schemes and an architecture with increased parallelism which considerably reduces the CORDIC latency time and the amount of hardware is described.
109
A new addition scheme and fast scaling factor compensation methods for CORDIC algorithms
TL;DR: This work presents speed enhancement techniques for CORDIC algorithms, covering algorithmic and implementation issues, and discusses speed limiting issues, namely addition techniques, appropriate number systems and scaling factor compensation with special emphasis on low latency time.
37
A programmable CORDIC chip for digital signal processing applications
TL;DR: The authors designed, fabricated, and tested a general-purpose fully parallel programmable CORDIC chip in CMOS technology and developed optimal iteration sequences.
32
A Low-Latency Pipelined 2D and 3D CORDIC Processors
TL;DR: This work improves the linear approximation scheme, leading to a unified implementation for rotation and vectoring, where fully parallel tree multipliers are used instead of the second half of CORDIC iterations.
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A 400-MHz processor for the conversion of rectangular to polar coordinates in 0.25-/spl mu/m CMOS
TL;DR: The architecture core uses small lookup ROMs, fast multipliers, and a single angle-rotation stage for a rectangular-to-polar coordinate converter for digital communication applications that reduces area and latency in comparison with traditional methods.
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References
•Book
Signal processing algorithms and architectures
Hassan Masud Ahmed
- 01 Jan 1982
TL;DR: The goal of the present work is to efficiently map algorithms onto architectures by maintaining a close link with the theoretical basis of a particular signal processing method by exploiting the ability to design a powerful signal processing chip capable of efficiently implementing such popular algorithms as the discrete Fourier transform, ladder filters and associated matrix algebra operations.
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