Model refinement for hardware-software codesign
Jie Gong,Daniel D. Gajski,Smita Bakshi +2 more
- 11 Mar 1996
- pp 270-274
21
TL;DR: This paper categorize several commonly-used implementation models and then describes a set of refinement procedures to transform a specification to each of these implementation models.
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Abstract: The model refinement task in system-level synthesis transforms a specification from a functional model to a chosen implementation model. In this paper, we categorize several commonly-used implementation models and then describe a set of refinement procedures to transform a specification to each of these implementation models. We also present a set of experimental results to compare the implementation models and to demonstrate how the proposed approach is used to explore different implementation styles.
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Citations
SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design
TL;DR: The SpecSyn system-level design environment is presented, which supports the new specify-explore-refine (SER) design paradigm, and the new paradigm and environment are expected to lead to a more than ten times reduction in design time.
Protocol selection and interface generation for HW-SW codesign
TL;DR: A new algorithm that performs binding/allocation of communication units is presented that makes use of a cost function to evaluate different allocation alternatives and illustrates through an example the usefulness of the algorithm for allocating automatically different protocols within the same application system.
87
VHDL generation from SDL specifications
Jean-Marc Daveau,G. F. Marchioro,Carlos Valderrama,Ahmed Amine Jerraya +3 more
- 01 Jun 2001
TL;DR: In this article, the authors present an approach that allows the generation of VHDL from system level specifications in SDL using an intermediate form that supports a powerful communication model which enables the representation in a synthesis oriented manner of most communication schemes.
A formal method for hardware IP design and integration under I/O and timing constraints
TL;DR: This paper proposes a set of techniques dedicated to the digital signal processing domain that lead to an optimized IP core integration and shows the effectiveness of the approach with a DCT core design case study.
30
System-level exploration with SpecSyn
Daniel D. Gajski,Frank Vahid,Sanjiv Narayan,Jie Gong +3 more
- 01 May 1998
TL;DR: Focusing on SpecSyn's exploration techniques, this work emphasizes its two-phase estimation approach and highlights experiments using SpecSyn.
29
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Sanjiv Narayan,Daniel D. Gajski +1 more
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Synthesis of the hardware/software interface in microcontroller-based systems
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Rapid-prototyping of hardware and software in a unified framework
Mani Srivastava,Robert W. Brodersen +1 more
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Hardware-software cosynthesis for digital systems
Rajesh Gupta,G. De Micheli +1 more
TL;DR: The authors demonstrate the feasibility of synthesizing heterogeneous systems by using timing constraints to delegate tasks between hardware and software so that performance requirements can be met.
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