Mis semiconductor device

TL;DR: In this article, an n+ contact area was formed on a first epitaxial layer which is piled up on a low-resistance n+ semiconductor substrate, and then an n- buffer layer and a p+ collector layer were formed on the surface of the n- drift layer.

Abstract: PROBLEM TO BE SOLVED: To improve the trade off relation between on-voltage and turn-off loss of an MIS semiconductor device such as IGBT, etc. SOLUTION: An n+ contact area 7 and a p+ contact area 8 are formed on a first epitaxial layer which is piled up on a low-resistance n+ semiconductor substrate 1. An n+ emitter area 14, a p base area 16, and an n- channel area 15 are formed in a second epitaxial layer. A polysilicon gate electrode 18 is formed on the emitter area 14 and base area 16 with a gate insulation film interposed, and it is covered with insulation films 19 and 20. An n- drift layer 21 is formed on the surface of the channel area 15 by epitaxial growth in the horizontal direction (ELO). Then an n- buffer layer 22 and a p+ collector layer 23 are formed on the surface of the n- drift layer 21. Such a formation process improves the strength of a thin-film collector IGBT, thus permitting easy processing. In addition, it can avoid the lamination step of a bidirectional IGBT and ease processing while keeping its mechanical strength.