Patent
Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells
Fatma Arzum Simsek-Ege,Aaron R. Wilson +1 more
- 15 Mar 2013
138
TL;DR: In this article, a metal-containing material is formed over a stack of alternating first and second levels and cavities are formed to extend into the conductively-doped silicon levels along sidewalls of the first opening.
read more
Abstract: Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. An opening is formed through the metal-containing material and the stack. Repeating vertically-stacked electrical components are formed along the stack at sidewalls of the opening. Some embodiments include a method of forming vertically-stacked memory cells. Metal-containing material is formed over a stack of alternating silicon dioxide levels and conductively-doped silicon levels. A first opening is formed through the metal-containing material and the stack. Cavities are formed to extend into the conductively-doped silicon levels along sidewalls of the first opening. Charge-blocking dielectric and charge-storage structures are formed within the cavities to leave a second opening. Sidewalls of the second opening are lined with gate dielectric and then channel material is formed within the second opening.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
Patent
High temperature chuck for plasma processing systems
Toan Q. Tran,Malik Sultan,Dmitry Lubomirsky,Shambhu N. Roy,Kobayashi Satoru,Tae Seung Cho,Soonam Park,Shankar Venkataraman +7 more
- 03 Feb 2015
TL;DR: In this article, a wafer chuck assembly includes a puck, a shaft and a base, where a heater element is embedded within the puck, and a conductive plate lies beneath the insulating material.
72
Patent
Thermal management systems and methods for wafer processing systems
Benjaminson David,Dmitry Lubomirsky +1 more
- 06 Aug 2015
TL;DR: In this paper, a workpiece holder includes a puck having a cylindrical axis, a radius about the diameter of the puck, and a thickness that is at least one-half of the radius of the ball.
70
Patent
Bolted wafer chuck thermal management systems and methods for wafer processing systems
Benjaminson David,Dmitry Lubomirsky,Ananda Seelavanth Math,Saravanakumar Natarajan,Shubham Chourey +4 more
- 06 Aug 2015
TL;DR: In this paper, a workpiece holder includes a puck, first and second heating devices in thermal communication with respective inner and outer portions of the puck, and a thermal sink in thermal communications with the puck.
70
Patent
Selective etch using material modification and rf pulsing
Citla Bhargav S,Ying Chentsau,Srinivas D. Nemani,Viachslav Babayan,Michael W. Stowell +4 more
- 29 Jun 2016
TL;DR: In this article, a low-power plasma may be formed by an RF bias power operating between about 10 W and about 100 W in embodiments, and the bias power may also be pulsed at a frequency below about 5,000 Hz.
58
Patent
Removal methods for high aspect ratio structures
Lin Xu,Zhijun Chen,Jiayin Huang,Anchuan Wang +3 more
- 11 Nov 2016
TL;DR: In this paper, a fluorine-containing precursor is inserted into a semiconductor processing chamber to generate plasma effluents of the precursors of the fluorine containing precursor.
57
References
Patent
Nonvolatile semiconductor memory device and manufacturing method thereof
Kato Juri
- 27 Sep 2006
TL;DR: A nonvolatile semiconductor memory device includes a gate electrode provided on a channel region of a semiconductor layer and a floating gate provided on the back side of the semiconductor layers with a first insulating layer interposed there between as discussed by the authors.
641
Patent
Three dimensional semiconductor memory devices and methods of fabricating the same
Kwang Soo Seol,Chanjin Park,Ki-Hyun Hwang,Han-mei Choi,Sunghoi Hur,Wan Sik Hwang,Toshiro Nakanishi,Kwangmin Park,Juyul Lee +8 more
- 12 Mar 2013
TL;DR: In this article, the three-dimensional semiconductor memory devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor pattern and the electrode structures.
526
Patent
Ultrahigh density vertical nand memory device and method of making thereof
Johann Alsmeier
- 05 Nov 2012
TL;DR: In this paper, the authors present a three-dimensional NAND string with a semiconductor channel, at least one end portion of the channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the substrate, and a tunnel dielectric located between each one of the discrete charge storage segments and the semiconductor channels.
504
Patent
Nonvolatile semiconductor memory device and method for manufacturing same
Shigeki Hattori,Reika Ichihara,Masaya Terai,Hideyuki Nishizawa,Tsukasa Tada,Koji Asakawa,Hiroyuki Fuke,Satoshi Mikoshiba,Yoshiaki Fukuzumi,Hideaki Aochi +9 more
- 19 Mar 2010
TL;DR: In this article, a nonvolatile semiconductor memory device, including a stacked structural unit including a plurality of insulating films alternately stacked with a multiplicity of electrode films in a first direction, is described.
450
Patent
Nonvolatile semiconductor memory
Sato Hiroshi,Noda Satoshi,Manita Kiichi,Kubono Shoji,Shigematsu Koji +4 more
- 17 Jan 2002
TL;DR: In this paper, the authors present an internal booster with a voltage detecting circuit (limiter LM) for detecting whether a boosted voltage has reached a predetermined potential or not and a timer capable of counting predetermined time.
405