Patent
Method for simulating hardware
David J. Greaves,Daryl Stewart +1 more
- 09 Jan 2006
22
TL;DR: In this article, a method for modifying hardware simulation having one internal timing regime to enable interoperation with another simulation having a different internal time regime is described, where variables are used so that they are interoperable with models in a domain using signals.
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Abstract: Integrated circuit design often involves combination of blocks of circuit from different sources to create new designs. However, a simulation of a block developed using a given method may not be compatible with another simulation created using another method. A method for modifying hardware simulation having one internal timing regime to enable interoperation with another simulation having a different internal timing regime is described. In particular, it involves modification of models in a domain in which variables are used so that they are interoperable with models in a domain using signals.
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Citations
Patent
RaceCheck: a race logic analyzer program for digital integrated circuits
Terence Wai-kwok Chan
- 22 Sep 2005
TL;DR: RaceCheck as mentioned in this paper audits IC designs for race logic design errors, using both structural and timing information of IC designs to filter out false violations, detecting concurrent invocation races of system and user-defined functions and tasks, and the use of a HDL simulation kernel for dynamic race logic analysis.
32
Patent
Configuring of intelligent electronic device
Shanka Gopinath Kishan
- 10 Sep 2007
TL;DR: In this article, a method of configuring an intelligent electronic device is presented, where a group of function blocks defining at least a part of a configuration of an intelligent device is provided, connection lines between the function blocks are defined, a fixed function block having a fixed cycle time value is located in the group of functions, and setting a configuration setting for a function block that is connected to the fixed function blocks is performed.
19
Patent
Method and system for verifying the equivalence of digital circuits
Tobias Gemmeke,Jens Leenstra,Nicolas Maeding,Hari Mony +3 more
- 12 Mar 2007
TL;DR: In this paper, the authors compare logic designs implemented in different hardware description languages (HDLs) and different design methodologies are compared by adding special wrappers (Wrapper A, Wrapper B) and used to equalize the timing of pairs of selected input signals and selected output signals of the logic designs.
18
Patent
Methods and apparatus for validating design changes
Yzhar Keysar,Anatoli Shindler,Yuri Miroshnik +2 more
- 11 Apr 2006
TL;DR: In this article, the authors propose a method for validating design changes in an integrated circuit design without propagating the effects of individual design changes to every location in the integrated circuit.
17
Patent
Sequential equivalence checking for asynchronous verification
Jason R. Baumgartner,Yee Ja,Hari Mony,Viresh Paruthi,Barinjato Ramanandray +4 more
- 27 Nov 2007
TL;DR: In this article, a model of the integrated circuit design has additional logic in it to reflect the possible variance in behavior of the asynchronous crossings, and sequential equivalence checking is performed to verify that the two models are input/output equivalent.
17
References
Patent
Simulation method and compiler for hardware/software programming
David J. Greaves
- 21 Jun 2001
TL;DR: In this article, a method for converting a hardware description language describing an integrated circuit or software operating thereon to an alternative programming language, such as ANSI C, C++, Java, or other object-oriented programming language is described.
25
Patent
Method and computer program product for software/hardware language model conversion
Noritaka Kawakatsu
- 31 Jan 2002
TL;DR: In this paper, the first model described in a software description language is converted into the second model describing in a hardware description language without considering whether a plurality of parallel procedures for writing with respect to the same shared variable are contained in the original model.
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