Patent
Method for performing error correction, associated memory apparatus and associated controller thereof
Ping-Yen Tsai
- 11 Aug 2014
11
TL;DR: In this paper, a method for performing error correction, an associated memory apparatus and an associated controller thereof are provided, where the data used in a hard decoding period can be wholly or partially reserved, and the reserved data can be used in soft decoding period.
read more
Abstract: A method for performing error correction, an associated memory apparatus and an associated controller thereof are provided. The data used in a hard decoding period can be wholly or partially reserved, and the reserved data can be used in a soft decoding period. For example, a read operation is performed at a specific physical address of a flash memory; after an uncorrectable error of the read operation is detected, a re-read operation is performed at the specific physical address of the flash memory to obtain first data and temporarily store the first data into a volatile memory, and a hard decoding operation is performed on the first data; and after decoding failure of the hard decoding operation is detected, a soft decoding operation is performed according to the first data read from the volatile memory to perform error correction corresponding to the specific physical address.
read more
Chat with Paper
AI Agents for this Paper
Find similar papers on Google Scholar, PubMed and Arxiv
Write a critical review of this paper
Analyze citations of this paper to find unaddressed research gaps
Citations
Patent
Flash memory apparatus and storage management method for flash memory
Tsung-Chieh Yang,Hong-Jung Hsu +1 more
- 25 Apr 2017
TL;DR: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple level-cell block such as MLC block, TLC block or QLC block.
26
Patent
Data storage device and operating method thereof
Hyeokjun Seo,Seok-Min Ko,Eui-Young Chung +2 more
- 25 Feb 2015
TL;DR: In this paper, an operating method of a data storage device including a plurality of nonvolatile memory devices includes the steps of: mapping physical addresses of the non-volatile memories into logical addresses, reflecting environmental factors to remap a physical address into a logical address requested to be accessed, and performing an interleaving operation for the nonvvolatile devices using the remapped physical address.
23
Patent
Method for accessing flash memory module and associated flash memory controller and memory device
Tsung-Chieh Yang,Hong-Jung Hsu +1 more
- 25 Apr 2017
TL;DR: In this article, a method for accessing a 3D flash memory module is presented, where each flash memory chip includes a plurality of blocks, each block includes a number of pages, and the method includes configuring the flash memory chips to set at least a first super block and at least another super block of the flash memories.
5
Patent
Flash memory error correction method and apparatus
Zeng Yanxing,Shen Jianqiang,Wang Gongyi +2 more
- 23 Jun 2020
TL;DR: A flash memory error correction method and apparatus is provided in this paper, where a first data bit in a flash memory page is determined, where the first data bits correspond to different data respectively in the data obtained by reading the flash memory pages using the (n+1)th read voltage threshold.
4
Patent
Fast decoding of data stored in a flash memory
Avi Steiner,Avigdor Segal,Hanan Weingarten +2 more
- 03 Mar 2016
TL;DR: In this article, the authors proposed a method for fast decoding, which may include (a) performing a hard read of a group of flash memory cells to provide hard read data; (b) performing at least one additional read attempt of the group to provide additional data; and (c) performing partial extensiveness soft decoding the additional data, in response to the first suggested values, to provide a soft decoding result.
4
References
Patent
Flash memory apparatus and methods using a plurality of decoding stages including optional use of concatenated BCH codes and/or designation of “first below” cells
Hanan Weingarten,Shmuel Levy,Michael Katz +2 more
- 17 Sep 2008
TL;DR: In this article, a method for decoding a plurality of flash memory cells which are error-correction-coded as a unit was proposed, the method comprising providing a hard decoding success indication indicating whether or not hard-decoding is at least likely to be successful.
297
Patent
Memory device with multiple-accuracy read commands
Uri Perlmutter,Ofir Shalvi,Yoav Kasorla,Naftali Sommer,Dotan Sokolov +4 more
- 17 Mar 2009
TL;DR: In this article, the first and second read commands for reading storage values from analog memory cells are defined and evaluated with respect to a read operation that is to be performed over a given group of the memory cells.
136
Patent
Soft decoding of hard and soft bits read from a flash memory
Idan Alrod,Eran Sharon,Simon Litsyn,Menahem Lasser +3 more
- 21 Dec 2006
TL;DR: In this paper, the threshold voltage of each flash memory cell is compared to at least one integral reference voltage and to a fractional reference voltage, and a respective estimated probability measure of each bit of an original bit pattern of each cell is calculated.
97
Patent
Method, memory controller and system for reading data stored in flash memory
Tsung-Chieh Yang
- 22 Feb 2012
TL;DR: In this paper, an exemplary method for reading data stored in a flash memory is presented. But this method requires the flash memory to perform a read operation upon a first page of the memory, obtaining a first codeword of the first page, and then performing an error correction operation according to the first set of LLR mapping values.
41
Patent
Soft Information Generation for Memory Systems
Ying Yu Tai,Yueh Yale Ma +1 more
- 10 Oct 2012
TL;DR: In this paper, a collection of characterization vectors that include soft information values for bit-tuples that may be read from a storage medium for various combinations of the storage medium characterization parameter values is presented.
36