Patent
Method for multiplexing bus interfaces on a computer expansion bus
Douglas A. Larson
- 04 Feb 1999
5
TL;DR: In this article, the PCI extension bus is coupled to a non-PCI device, such as a device normally connected to a relatively low speed bus, by an arbiter in the bus bridge.
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Abstract: A computer system includes a processor/PCI bus bridge that couples a processor bus to a relatively high-speed expansion bus, such as a PCI bus and a PCI extension bus. The PCI extension bus is coupled to a 32-bit PCI device, a 64-bit PCI device, and a non-PCI device, such as a device normally connected to a relatively low speed bus. In operation, an arbiter in the bus bridge selectively grants either the 64-bit PCI device or the non-PCI device access to the PCI extension bus. Data transfers between the processor bus and the non-PCI device can occur simultaneously with data transfers between the processor bus and the 32-bit PCI device. Several non-PCI devices may be coupled to the PCI extension bus. Data transfer between the processor bus and the non-PCI devices may be accomplished alternately if the non-PCI devices share the same lines of the PCI extension bus or simultaneously in the non-PCI devices use different lines of the PCI extension bus.
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Citations
Patent
Method and apparatus for buffering bi-directional open drain signal lines
Daniel J. Schwarz
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TL;DR: In this article, the authors propose a method of interfacing at least two components with different logic voltage requirements on a single bus without a separate directional control signal, using a logic adjusting circuit for translating a first logic level of a first component to a second logic levels of a second component.
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- 06 Jul 2000
TL;DR: In this article, the authors propose a secondary bus infrastructure to avoid data phase transaction latencies during primary bus information transfers, where a first bus is coupled to a host adapter and a plurality of media adapters.
6
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Jong-Min Seong Nak-Hee Kim You,Young-Duk Kim,Jae-Hong Park,Kwon Young Jun,Jong-Min Lee +4 more
- 03 Jul 2006
TL;DR: In this paper, an arbitrator coordinates access between the masters and the slaves via a single read/write bus path between the arbitrator and the first type of slave, and via a plurality of read bus paths and/or a pluralityof write bus paths between arbitrators and the second type of slaves.
5
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Yu-Lun Cheng,Chung-hung Tsai +1 more
- 24 Feb 2005
TL;DR: In this article, a pin sharing system for sharing with a peripheral device one of a plurality of pins configured between an ATA device and an I/O device is described, where the ATA controller is used for receiving a signal, transmitted via the pins, from the peripheral device and for detecting the status of the shared pin to generate a status signal.
4
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Bruce L. Fleming,Achmed R. Zahir,Arvind Mandhani,Satish B. Acharya +3 more
- 24 Sep 2012
TL;DR: In this paper, an embodiment integrates non-PCIPCI compliant devices with PCI compliant operating systems. But, the authors do not specify the architecture of the non-IoT devices.
3
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